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lxdream.org :: lxdream/src/sh4/sh4mmio.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.c
changeset 23:1ec3acd0594d
prev19:9da7a8e38f9d
next30:89b30313d757
author nkeynes
date Fri Dec 23 11:44:55 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Start of "real" time slices, general structure in place now
file annotate diff log raw
1.1 --- a/src/sh4/sh4mmio.c Thu Dec 22 07:38:12 2005 +0000
1.2 +++ b/src/sh4/sh4mmio.c Fri Dec 23 11:44:55 2005 +0000
1.3 @@ -134,97 +134,12 @@
1.4
1.5 MMIO_REGION_STUBFNS( UBC )
1.6
1.7 -/********************************* CPG *************************************/
1.8 -
1.9 -uint32_t sh4_freq = SH4_BASE_RATE;
1.10 -uint32_t sh4_bus_freq = SH4_BASE_RATE;
1.11 -uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
1.12 -
1.13 -
1.14 -MMIO_REGION_STUBFNS( CPG )
1.15
1.16 /********************************* DMAC *************************************/
1.17
1.18 MMIO_REGION_STUBFNS( DMAC )
1.19
1.20 -/********************************** RTC *************************************/
1.21
1.22 -MMIO_REGION_STUBFNS( RTC )
1.23 -
1.24 -/********************************** TMU *************************************/
1.25 -
1.26 -int timer_divider[3] = {16,16,16};
1.27 -MMIO_REGION_READ_DEFFN( TMU )
1.28 -
1.29 -int get_timer_div( int val )
1.30 -{
1.31 - switch( val & 0x07 ) {
1.32 - case 0: return 16; /* assume peripheral clock is IC/4 */
1.33 - case 1: return 64;
1.34 - case 2: return 256;
1.35 - case 3: return 1024;
1.36 - case 4: return 4096;
1.37 - }
1.38 - return 1;
1.39 -}
1.40 -
1.41 -void mmio_region_TMU_write( uint32_t reg, uint32_t val )
1.42 -{
1.43 - switch( reg ) {
1.44 - case TCR0:
1.45 - timer_divider[0] = get_timer_div(val);
1.46 - break;
1.47 - case TCR1:
1.48 - timer_divider[1] = get_timer_div(val);
1.49 - break;
1.50 - case TCR2:
1.51 - timer_divider[2] = get_timer_div(val);
1.52 - break;
1.53 - }
1.54 - MMIO_WRITE( TMU, reg, val );
1.55 -}
1.56 -
1.57 -void run_timers( int cycles )
1.58 -{
1.59 - int tcr = MMIO_READ( TMU, TSTR );
1.60 - cycles *= 16;
1.61 - if( tcr & 0x01 ) {
1.62 - int count = cycles / timer_divider[0];
1.63 - int *val = MMIO_REG( TMU, TCNT0 );
1.64 - if( *val < count ) {
1.65 - MMIO_READ( TMU, TCR0 ) |= 0x100;
1.66 - /* interrupt goes here */
1.67 - count -= *val;
1.68 - *val = MMIO_READ( TMU, TCOR0 ) - count;
1.69 - } else {
1.70 - *val -= count;
1.71 - }
1.72 - }
1.73 - if( tcr & 0x02 ) {
1.74 - int count = cycles / timer_divider[1];
1.75 - int *val = MMIO_REG( TMU, TCNT1 );
1.76 - if( *val < count ) {
1.77 - MMIO_READ( TMU, TCR1 ) |= 0x100;
1.78 - /* interrupt goes here */
1.79 - count -= *val;
1.80 - *val = MMIO_READ( TMU, TCOR1 ) - count;
1.81 - } else {
1.82 - *val -= count;
1.83 - }
1.84 - }
1.85 - if( tcr & 0x04 ) {
1.86 - int count = cycles / timer_divider[2];
1.87 - int *val = MMIO_REG( TMU, TCNT2 );
1.88 - if( *val < count ) {
1.89 - MMIO_READ( TMU, TCR2 ) |= 0x100;
1.90 - /* interrupt goes here */
1.91 - count -= *val;
1.92 - *val = MMIO_READ( TMU, TCOR2 ) - count;
1.93 - } else {
1.94 - *val -= count;
1.95 - }
1.96 - }
1.97 -}
1.98
1.99 /********************************** SCI *************************************/
1.100
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