1.1 --- a/test/dmac.c	Tue Jan 01 05:08:38 2008 +0000
     1.2 +++ b/test/dmac.c	Sun Jul 20 11:36:48 2008 +0000
     1.3 @@ -33,6 +33,13 @@
     1.4  #define PVR_DMA_CTL   (ASIC_BASE+0x808)
     1.5  #define PVR_DMA_REGION (ASIC_BASE+0x884)
     1.6  
     1.7 +#define SORT_DMA_TABLE (ASIC_BASE+0x810)
     1.8 +#define SORT_DMA_DATA  (ASIC_BASE+0x814)
     1.9 +#define SORT_DMA_TABLEBITS (ASIC_BASE+0x818)
    1.10 +#define SORT_DMA_DATASIZE (ASIC_BASE+0x81C)
    1.11 +#define SORT_DMA_CTL   (ASIC_BASE+0x820)
    1.12 +#define SORT_DMA_COUNT (ASIC_BASE+0x860)
    1.13 +
    1.14  void dmac_dump_channel( FILE *f, unsigned int channel )
    1.15  {
    1.16      fprintf( f, "DMAC SAR: %08X  Count: %08X  Ctl: %08X  OR: %08X\n",
    1.17 @@ -124,3 +131,29 @@
    1.18  
    1.19      return result;
    1.20  }
    1.21 +
    1.22 +int sort_dma_write( char *sorttable, int tablelen, char *data, int datalen, int bitwidth, int datasize )
    1.23 +{
    1.24 +    int result;
    1.25 +    uint32_t tableaddr = (uint32_t)sorttable;
    1.26 +    uint32_t dataaddr = (uint32_t)data;
    1.27 +    
    1.28 +    long_write( SORT_DMA_CTL, 0 );
    1.29 +    asic_clear();
    1.30 +    
    1.31 +    long_write( SORT_DMA_TABLE, tableaddr );
    1.32 +    long_write( SORT_DMA_DATA, dataaddr );
    1.33 +    long_write( SORT_DMA_TABLEBITS, bitwidth );
    1.34 +    long_write( SORT_DMA_DATASIZE, datasize );
    1.35 +    long_write( SORT_DMA_CTL, 1 );
    1.36 +    result = asic_wait2(EVENT_SORT_DMA, EVENT_SORT_DMA_ERR);
    1.37 +    if( result == -1 ) {
    1.38 +        fprintf( stderr, "SORT DMA failed (timeout)\n" );
    1.39 +        asic_dump(stderr);
    1.40 +        fprintf( stderr, "Table: %08X Count: %08X Ctl: %08X\n", long_read(SORT_DMA_TABLE), long_read(SORT_DMA_COUNT),
    1.41 +                 long_read(SORT_DMA_CTL) );
    1.42 +        long_write( SORT_DMA_CTL, 0 );
    1.43 +    }
    1.44 +    CHECK_IEQUALS( 0, long_read(SORT_DMA_CTL) );
    1.45 +    return result;
    1.46 +}