filename | src/aica/aica.c |
changeset | 35:21a4be098304 |
prev | 30:89b30313d757 |
next | 37:1d84f4c18816 |
author | nkeynes |
date | Mon Dec 26 03:54:55 2005 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Remove modules.h - move definitions into dream.h Add source string to output list (taken from module name) ARM Work in progress |
file | annotate | diff | log | raw |
1.1 --- a/src/aica/aica.c Sun Dec 25 05:57:00 2005 +00001.2 +++ b/src/aica/aica.c Mon Dec 26 03:54:55 2005 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: aica.c,v 1.5 2005-12-25 05:57:00 nkeynes Exp $1.6 + * $Id: aica.c,v 1.6 2005-12-26 03:54:55 nkeynes Exp $1.7 *1.8 * This is the core sound system (ie the bit which does the actual work)1.9 *1.10 @@ -16,8 +16,9 @@1.11 * GNU General Public License for more details.1.12 */1.14 +#define MODULE aica_module1.15 +1.16 #include "dream.h"1.17 -#include "modules.h"1.18 #include "mem.h"1.19 #include "aica.h"1.20 #define MMIO_IMPL1.21 @@ -31,12 +32,14 @@1.22 void aica_reset( void );1.23 void aica_start( void );1.24 void aica_stop( void );1.25 +void aica_save_state( FILE *f );1.26 +int aica_load_state( FILE *f );1.27 uint32_t aica_run_slice( uint32_t );1.30 struct dreamcast_module aica_module = { "AICA", aica_init, aica_reset,1.31 aica_start, aica_run_slice, aica_stop,1.32 - NULL, NULL, NULL };1.33 + aica_save_state, aica_load_state };1.35 /**1.36 * Initialize the AICA subsystem. Note requires that1.37 @@ -51,7 +54,7 @@1.39 void aica_reset( void )1.40 {1.41 -1.42 + arm_reset();1.43 }1.45 void aica_start( void )1.46 @@ -62,6 +65,11 @@1.47 uint32_t aica_run_slice( uint32_t nanosecs )1.48 {1.49 /* Run arm instructions */1.50 + int reset = MMIO_READ( AICA2, AICA_RESET );1.51 + if( reset & 1 == 0 ) {1.52 + /* Running */1.53 + /* nanosecs = arm_run_slice( nanosecs ); */1.54 + }1.55 /* Generate audio buffer */1.56 }1.58 @@ -70,6 +78,16 @@1.60 }1.62 +void aica_save_state( FILE *f )1.63 +{1.64 + arm_save_state( f );1.65 +}1.66 +1.67 +int aica_load_state( FILE *f )1.68 +{1.69 + return arm_load_state( f );1.70 +}1.71 +1.72 /** Channel register structure:1.73 * 001.74 * 041.75 @@ -94,6 +112,7 @@1.76 void mmio_region_AICA0_write( uint32_t reg, uint32_t val )1.77 {1.78 // aica_write_channel( reg >> 7, reg % 128, val );1.79 + MMIO_WRITE( AICA0, reg, val );1.81 }1.83 @@ -101,11 +120,25 @@1.84 void mmio_region_AICA1_write( uint32_t reg, uint32_t val )1.85 {1.86 // aica_write_channel( (reg >> 7) + 32, reg % 128, val );1.87 -1.88 + MMIO_WRITE( AICA1, reg, val );1.89 }1.91 /* General registers */1.92 void mmio_region_AICA2_write( uint32_t reg, uint32_t val )1.93 {1.94 -1.95 + uint32_t tmp;1.96 + switch( reg ) {1.97 + case AICA_RESET:1.98 + tmp = MMIO_READ( AICA2, AICA_RESET );1.99 + if( tmp & 1 == 1 && val & 1 == 0 ) {1.100 + /* ARM enabled - execute a core reset */1.101 + INFO( "ARM enabled" );1.102 + arm_reset();1.103 + }1.104 + MMIO_WRITE( AICA2, AICA_RESET, val );1.105 + break;1.106 + default:1.107 + MMIO_WRITE( AICA2, reg, val );1.108 + break;1.109 + }1.110 }
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