1.1 --- a/src/aica/armcore.h	Sun Dec 25 05:57:00 2005 +0000
     1.2 +++ b/src/aica/armcore.h	Mon Dec 26 03:54:55 2005 +0000
     1.3 @@ -1,5 +1,5 @@
     1.4  /**
     1.5 - * $Id: armcore.h,v 1.6 2005-12-25 05:57:00 nkeynes Exp $
     1.6 + * $Id: armcore.h,v 1.7 2005-12-26 03:54:55 nkeynes Exp $
     1.7   * 
     1.8   * Interface definitions for the ARM CPU emulation core proper.
     1.9   *
    1.10 @@ -21,6 +21,11 @@
    1.11  
    1.12  #include "dream.h"
    1.13  #include <stdint.h>
    1.14 +#include <stdio.h>
    1.15 +
    1.16 +#define ARM_BASE_RATE 33 /* MHZ */
    1.17 +extern uint32_t arm_cpu_freq;
    1.18 +extern uint32_t arm_cpu_period;
    1.19  
    1.20  #define ROTATE_RIGHT_LONG(operand,shift) ((((uint32_t)operand) >> shift) | ((operand<<(32-shift))) )
    1.21  
    1.22 @@ -30,13 +35,16 @@
    1.23      uint32_t cpsr;
    1.24      uint32_t spsr;
    1.25      
    1.26 -    /* Various banked versions of the registers. */
    1.27 -    uint32_t fiq_r[7]; /* FIQ bank 8..14 */
    1.28 -    uint32_t irq_r[2]; /* IRQ bank 13..14 */
    1.29 -    uint32_t und_r[2]; /* UND bank 13..14 */
    1.30 -    uint32_t abt_r[2]; /* ABT bank 13..14 */
    1.31 -    uint32_t svc_r[2]; /* SVC bank 13..14 */
    1.32 +    /* Various banked versions of the registers. Note that these are used
    1.33 +     * to save the registers for the named bank when leaving the mode, they're
    1.34 +     * not actually used actively.
    1.35 +     **/
    1.36      uint32_t user_r[7]; /* User/System bank 8..14 */
    1.37 +    uint32_t svc_r[3]; /* SVC bank 13..14, SPSR */
    1.38 +    uint32_t abt_r[3]; /* ABT bank 13..14, SPSR */
    1.39 +    uint32_t und_r[3]; /* UND bank 13..14, SPSR */
    1.40 +    uint32_t irq_r[3]; /* IRQ bank 13..14, SPSR */
    1.41 +    uint32_t fiq_r[8]; /* FIQ bank 8..14, SPSR */
    1.42      
    1.43      uint32_t c,n,z,v,t;
    1.44      
    1.45 @@ -54,18 +62,25 @@
    1.46  #define CPSR_T 0x00000020 /* Thumb mode */
    1.47  #define CPSR_MODE 0x0000001F /* Current execution mode */
    1.48  
    1.49 -#define MODE_USER 0x00 /* User mode */
    1.50 -#define MODE_FIQ   0x01 /* Fast IRQ mode */
    1.51 -#define MODE_IRQ  0x02 /* IRQ mode */
    1.52 -#define MODE_SV   0x03 /* Supervisor mode */
    1.53 -#define MODE_ABT 0x07 /* Abort mode */
    1.54 -#define MODE_UND 0x0B /* Undefined mode */
    1.55 -#define MODE_SYS 0x0F /* System mode */
    1.56 +#define MODE_USER 0x10 /* User mode */
    1.57 +#define MODE_FIQ   0x11 /* Fast IRQ mode */
    1.58 +#define MODE_IRQ  0x12 /* IRQ mode */
    1.59 +#define MODE_SVC  0x13 /* Supervisor mode */
    1.60 +#define MODE_ABT 0x17 /* Abort mode */
    1.61 +#define MODE_UND 0x1B /* Undefined mode */
    1.62 +#define MODE_SYS 0x1F /* System mode */
    1.63  
    1.64  extern struct arm_registers armr;
    1.65  
    1.66  #define CARRY_FLAG (armr.cpsr&CPSR_C)
    1.67  
    1.68 +/* ARM core functions */
    1.69 +void arm_reset( void );
    1.70 +uint32_t arm_run_slice( uint32_t nanosecs );
    1.71 +void arm_save_state( FILE *f );
    1.72 +int arm_load_state( FILE *f );
    1.73 +gboolean arm_execute_instruction( void );
    1.74 +
    1.75  /* ARM Memory */
    1.76  int32_t arm_read_long( uint32_t addr );
    1.77  int32_t arm_read_word( uint32_t addr );
    1.78 @@ -75,6 +90,5 @@
    1.79  void arm_write_byte( uint32_t addr, uint32_t val );
    1.80  int32_t arm_read_phys_word( uint32_t addr );
    1.81  int arm_has_page( uint32_t addr );
    1.82 -gboolean arm_execute_instruction( void );
    1.83  
    1.84  #endif /* !dream_armcore_H */