1.1 --- a/src/pvr2/pvr2.c	Tue Mar 14 13:02:06 2006 +0000
     1.2 +++ b/src/pvr2/pvr2.c	Thu Mar 16 12:41:59 2006 +0000
     1.3 @@ -1,5 +1,5 @@
     1.4  /**
     1.5 - * $Id: pvr2.c,v 1.19 2006-03-14 13:02:06 nkeynes Exp $
     1.6 + * $Id: pvr2.c,v 1.20 2006-03-15 13:16:50 nkeynes Exp $
     1.7   *
     1.8   * PVR2 (Video) Core MMIO registers.
     1.9   *
    1.10 @@ -44,12 +44,12 @@
    1.11  struct video_timing {
    1.12      int fields_per_second;
    1.13      int total_lines;
    1.14 -    int display_lines;
    1.15 +    int retrace_lines;
    1.16      int line_time_ns;
    1.17  };
    1.18  
    1.19 -struct video_timing pal_timing = { 50, 625, 575, 32000 };
    1.20 -struct video_timing ntsc_timing= { 60, 525, 480, 31746 };
    1.21 +struct video_timing pal_timing = { 50, 625, 50, 32000 };
    1.22 +struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
    1.23  
    1.24  struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL, 
    1.25  					pvr2_run_slice, NULL,
    1.26 @@ -74,12 +74,15 @@
    1.27      if( driver->init_driver != NULL )
    1.28  	driver->init_driver();
    1.29      driver->set_display_format( 640, 480, COLFMT_RGB32 );
    1.30 +    driver->set_render_format( 640, 480, COLFMT_RGB32, FALSE );
    1.31 +    texcache_gl_init();
    1.32  }
    1.33  
    1.34  uint32_t pvr2_line_count = 0;
    1.35  uint32_t pvr2_line_remainder = 0;
    1.36  uint32_t pvr2_irq_vpos1 = 0;
    1.37  uint32_t pvr2_irq_vpos2 = 0;
    1.38 +gboolean pvr2_retrace = FALSE;
    1.39  struct video_timing *pvr2_timing = &ntsc_timing;
    1.40  uint32_t pvr2_time_counter = 0;
    1.41  uint32_t pvr2_frame_counter = 0;
    1.42 @@ -97,11 +100,15 @@
    1.43  	if( pvr2_line_count == pvr2_irq_vpos2 ) {
    1.44  	    asic_event( EVENT_SCANLINE2 );
    1.45  	}
    1.46 -	if( pvr2_line_count == pvr2_timing->display_lines ) {
    1.47 +	if( pvr2_line_count == pvr2_timing->total_lines ) {
    1.48  	    asic_event( EVENT_RETRACE );
    1.49 -	} else if( pvr2_line_count == pvr2_timing->total_lines ) {
    1.50 -	    pvr2_display_frame();
    1.51  	    pvr2_line_count = 0;
    1.52 +	    pvr2_retrace = TRUE;
    1.53 +	} else if( pvr2_line_count == pvr2_timing->retrace_lines ) {
    1.54 +	    if( pvr2_retrace ) {
    1.55 +		pvr2_display_frame();
    1.56 +		pvr2_retrace = FALSE;
    1.57 +	    }
    1.58  	}
    1.59      }
    1.60      return nanosecs;
    1.61 @@ -189,8 +196,16 @@
    1.62      
    1.63      INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, 
    1.64            MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
    1.65 +
    1.66 +    MMIO_WRITE( PVR2, reg, val );
    1.67     
    1.68      switch(reg) {
    1.69 +    case DISPADDR1:
    1.70 +	if( pvr2_retrace ) {
    1.71 +	    pvr2_display_frame();
    1.72 +	    pvr2_retrace = FALSE;
    1.73 +	}
    1.74 +	break;
    1.75      case VPOS_IRQ:
    1.76  	pvr2_irq_vpos1 = (val >> 16) & 0x03FF;
    1.77  	pvr2_irq_vpos2 = val & 0x03FF;
    1.78 @@ -204,7 +219,6 @@
    1.79  	    pvr2_render_scene();
    1.80  	break;
    1.81      }
    1.82 -    MMIO_WRITE( PVR2, reg, val );
    1.83  }
    1.84  
    1.85  MMIO_REGION_READ_FN( PVR2, reg )
    1.86 @@ -254,8 +268,10 @@
    1.87  	texcache_invalidate_page( i );
    1.88      }
    1.89  
    1.90 -    banks[0] = ((uint32_t *)(video_base + (destaddr>>3)));
    1.91 +    banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
    1.92      banks[1] = banks[0] + 0x100000;
    1.93 +    if( bank_flag ) 
    1.94 +	banks[0]++;
    1.95      
    1.96      /* Handle non-aligned start of source */
    1.97      if( destaddr & 0x03 ) {
    1.98 @@ -295,8 +311,10 @@
    1.99      if( srcaddr + length > 0x800000 )
   1.100  	length = 0x800000 - srcaddr;
   1.101  
   1.102 -    banks[0] = ((uint32_t *)(video_base + (srcaddr>>3)));
   1.103 +    banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
   1.104      banks[1] = banks[0] + 0x100000;
   1.105 +    if( bank_flag )
   1.106 +	banks[0]++;
   1.107      
   1.108      /* Handle non-aligned start of source */
   1.109      if( srcaddr & 0x03 ) {