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lxdream.org :: lxdream/src/sh4/sh4dasm.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4dasm.c
changeset 9:2784c7660165
prev2:42349f6ea216
next10:c898b37506e0
author nkeynes
date Thu Dec 08 13:38:00 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Generalise the core debug window to allow multiple instances.
Add cpu description structure to define different cpus for use by the
debug window, in preparation for ARM implementation
file annotate diff log raw
1.1 --- a/src/sh4/sh4dasm.c Sat Aug 21 06:15:49 2004 +0000
1.2 +++ b/src/sh4/sh4dasm.c Thu Dec 08 13:38:00 2005 +0000
1.3 @@ -4,6 +4,29 @@
1.4
1.5 #define UNIMP(ir) snprintf( buf, len, "??? " )
1.6
1.7 +
1.8 +struct reg_desc_struct sh4_reg_map[] =
1.9 + { {"R0", REG_INT, &sh4r.r[0]}, {"R1", REG_INT, &sh4r.r[1]},
1.10 + {"R2", REG_INT, &sh4r.r[2]}, {"R3", REG_INT, &sh4r.r[3]},
1.11 + {"R4", REG_INT, &sh4r.r[4]}, {"R5", REG_INT, &sh4r.r[5]},
1.12 + {"R6", REG_INT, &sh4r.r[6]}, {"R7", REG_INT, &sh4r.r[7]},
1.13 + {"R8", REG_INT, &sh4r.r[8]}, {"R9", REG_INT, &sh4r.r[9]},
1.14 + {"R10",REG_INT, &sh4r.r[10]}, {"R11",REG_INT, &sh4r.r[11]},
1.15 + {"R12",REG_INT, &sh4r.r[12]}, {"R13",REG_INT, &sh4r.r[13]},
1.16 + {"R14",REG_INT, &sh4r.r[14]}, {"R15",REG_INT, &sh4r.r[15]},
1.17 + {"SR", REG_INT, &sh4r.sr}, {"GBR", REG_INT, &sh4r.gbr},
1.18 + {"SSR",REG_INT, &sh4r.ssr}, {"SPC", REG_INT, &sh4r.spc},
1.19 + {"SGR",REG_INT, &sh4r.sgr}, {"DBR", REG_INT, &sh4r.dbr},
1.20 + {"VBR",REG_INT, &sh4r.vbr},
1.21 + {"PC", REG_INT, &sh4r.pc}, {"PR", REG_INT, &sh4r.pr},
1.22 + {"MACL",REG_INT, &sh4r.mac},{"MACH",REG_INT, ((uint32_t *)&sh4r.mac)+1},
1.23 + {"FPUL", REG_INT, &sh4r.fpul}, {"FPSCR", REG_INT, &sh4r.fpscr},
1.24 + {NULL, 0, NULL} };
1.25 +
1.26 +struct cpu_desc_struct sh4_cpu_desc = { "SH4", sh4_disasm_instruction, 2,
1.27 + &sh4r, sizeof(sh4r), sh4_reg_map,
1.28 + &sh4r.pc, &sh4r.icount };
1.29 +
1.30 int sh4_disasm_instruction( int pc, char *buf, int len )
1.31 {
1.32 uint16_t ir = mem_read_word(pc);
.