1.1 --- a/src/sh4/sh4.c Sun Aug 24 01:40:58 2008 +0000
1.2 +++ b/src/sh4/sh4.c Tue Sep 02 11:53:50 2008 +0000
1.12 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
1.13 TMU_run_slice( sh4r.slice_cycle );
1.14 SCIF_run_slice( sh4r.slice_cycle );
1.15 + PMM_run_slice( sh4r.slice_cycle );
1.17 return sh4r.slice_cycle;
1.20 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
1.21 TMU_run_slice( nanosecs );
1.22 SCIF_run_slice( nanosecs );
1.23 + PMM_run_slice( sh4r.slice_cycle );
1.29 fwrite( &sh4r, sizeof(sh4r), 1, f );
1.30 MMU_save_state( f );
1.31 + PMM_save_state( f );
1.32 INTC_save_state( f );
1.33 TMU_save_state( f );
1.34 SCIF_save_state( f );
1.37 fread( &sh4r, sizeof(sh4r), 1, f );
1.38 MMU_load_state( f );
1.39 + PMM_load_state( f );
1.40 INTC_load_state( f );
1.41 TMU_load_state( f );
1.42 return SCIF_load_state( f );
1.44 /* Bring all running peripheral modules up to date, and then halt them. */
1.45 TMU_run_slice( sh4r.slice_cycle );
1.46 SCIF_run_slice( sh4r.slice_cycle );
1.47 + PMM_run_slice( sh4r.slice_cycle );
1.49 if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
1.50 sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;