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lxdream.org :: lxdream/src/sh4/sh4.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 586:2a3ba82cf243
prev526:ba3da45b5754
next591:7b9612fd2395
author nkeynes
date Tue Jan 15 20:50:23 2008 +0000 (14 years ago)
permissions -rw-r--r--
last change Merged lxdream-mmu r570:596 to trunk
file annotate diff log raw
1.1 --- a/src/sh4/sh4.c Sat Nov 17 06:04:19 2007 +0000
1.2 +++ b/src/sh4/sh4.c Tue Jan 15 20:50:23 2008 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4.c,v 1.7 2007-11-08 11:54:16 nkeynes Exp $
1.6 + * $Id$
1.7 *
1.8 * SH4 parent module for all CPU modes and SH4 peripheral
1.9 * modules.
1.10 @@ -30,10 +30,6 @@
1.11 #include "clock.h"
1.12 #include "syscall.h"
1.13
1.14 -#define EXV_EXCEPTION 0x100 /* General exception vector */
1.15 -#define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
1.16 -#define EXV_INTERRUPT 0x600 /* External interrupt vector */
1.17 -
1.18 void sh4_init( void );
1.19 void sh4_xlat_init( void );
1.20 void sh4_reset( void );
1.21 @@ -52,8 +48,9 @@
1.22 struct sh4_registers sh4r;
1.23 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
1.24 int sh4_breakpoint_count = 0;
1.25 -extern sh4ptr_t sh4_main_ram;
1.26 +sh4ptr_t sh4_main_ram;
1.27 static gboolean sh4_use_translator = FALSE;
1.28 +struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
1.29
1.30 void sh4_set_use_xlat( gboolean use )
1.31 {
1.32 @@ -70,6 +67,11 @@
1.33 #endif
1.34 }
1.35
1.36 +gboolean sh4_is_using_xlat()
1.37 +{
1.38 + return sh4_use_translator;
1.39 +}
1.40 +
1.41 void sh4_init(void)
1.42 {
1.43 register_io_regions( mmio_list_sh4mmio );
1.44 @@ -148,14 +150,17 @@
1.45 }
1.46
1.47
1.48 -void sh4_set_breakpoint( uint32_t pc, int type )
1.49 +void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
1.50 {
1.51 sh4_breakpoints[sh4_breakpoint_count].address = pc;
1.52 sh4_breakpoints[sh4_breakpoint_count].type = type;
1.53 + if( sh4_use_translator ) {
1.54 + xlat_invalidate_word( pc );
1.55 + }
1.56 sh4_breakpoint_count++;
1.57 }
1.58
1.59 -gboolean sh4_clear_breakpoint( uint32_t pc, int type )
1.60 +gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
1.61 {
1.62 int i;
1.63
1.64 @@ -166,6 +171,9 @@
1.65 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
1.66 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
1.67 }
1.68 + if( sh4_use_translator ) {
1.69 + xlat_invalidate_word( pc );
1.70 + }
1.71 sh4_breakpoint_count--;
1.72 return TRUE;
1.73 }
1.74 @@ -203,7 +211,9 @@
1.75
1.76 void sh4_write_sr( uint32_t newval )
1.77 {
1.78 - if( (newval ^ sh4r.sr) & SR_RB )
1.79 + int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
1.80 + int newbank = (newval&SR_MDRB) == SR_MDRB;
1.81 + if( oldbank != newbank )
1.82 sh4_switch_banks();
1.83 sh4r.sr = newval;
1.84 sh4r.t = (newval&SR_T) ? 1 : 0;
1.85 @@ -254,10 +264,25 @@
1.86 RAISE( code, EXV_EXCEPTION );
1.87 }
1.88
1.89 +/**
1.90 + * Raise a CPU reset exception with the specified exception code.
1.91 + */
1.92 +gboolean sh4_raise_reset( int code )
1.93 +{
1.94 + // FIXME: reset modules as per "manual reset"
1.95 + sh4_reset();
1.96 + MMIO_WRITE(MMU,EXPEVT,code);
1.97 + sh4r.vbr = 0;
1.98 + sh4r.pc = 0xA0000000;
1.99 + sh4r.new_pc = sh4r.pc + 2;
1.100 + sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
1.101 + &(~SR_FD) );
1.102 +}
1.103 +
1.104 gboolean sh4_raise_trap( int trap )
1.105 {
1.106 MMIO_WRITE( MMU, TRA, trap<<2 );
1.107 - return sh4_raise_exception( EXC_TRAP );
1.108 + RAISE( EXC_TRAP, EXV_EXCEPTION );
1.109 }
1.110
1.111 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
.