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lxdream.org :: lxdream/src/sh4/sh4mmio.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.c
changeset 312:2c34bdc36cbd
prev166:8aa70cf503a2
next323:067583c1a704
author nkeynes
date Tue Jan 23 08:17:06 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Save/restore MMU state (specifically the OC cache ram) correctly
file annotate diff log raw
1.1 --- a/src/sh4/sh4mmio.c Sun Jun 18 12:01:53 2006 +0000
1.2 +++ b/src/sh4/sh4mmio.c Tue Jan 23 08:17:06 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4mmio.c,v 1.9 2006-06-18 12:01:53 nkeynes Exp $
1.6 + * $Id: sh4mmio.c,v 1.10 2007-01-23 08:17:06 nkeynes Exp $
1.7 *
1.8 * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
1.9 * responsible for including the IMPL side of the SH4 MMIO pages.
1.10 @@ -49,11 +49,33 @@
1.11 }
1.12
1.13
1.14 -void mmu_init()
1.15 +void MMU_init()
1.16 {
1.17 cache = mem_alloc_pages(2);
1.18 }
1.19
1.20 +void MMU_reset()
1.21 +{
1.22 + mmio_region_MMU_write( CCR, 0 );
1.23 +}
1.24 +
1.25 +void MMU_save_state( FILE *f )
1.26 +{
1.27 + fwrite( cache, 4096, 2, f );
1.28 +}
1.29 +
1.30 +int MMU_load_state( FILE *f )
1.31 +{
1.32 + /* Setup the cache mode according to the saved register value
1.33 + * (mem_load runs before this point to load all MMIO data)
1.34 + */
1.35 + mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
1.36 + if( fread( cache, 4096, 2, f ) != 2 ) {
1.37 + return 1;
1.38 + }
1.39 + return 0;
1.40 +}
1.41 +
1.42 void mmu_set_cache_mode( int mode )
1.43 {
1.44 uint32_t i;
.