filename | src/pvr2/pvr2.h |
changeset | 315:2d8ba198d62c |
prev | 310:00cd8897ad5e |
next | 319:5392aed6a982 |
author | nkeynes |
date | Tue Jan 23 11:19:32 2007 +0000 (17 years ago) |
permissions | -rw-r--r-- |
last change | Refactor render buffer read/write to pvr2mem.c Implement 4-bit indexed textures (tentatively) Fix RGB24 support |
file | annotate | diff | log | raw |
1.1 --- a/src/pvr2/pvr2.h Mon Jan 22 11:45:37 2007 +00001.2 +++ b/src/pvr2/pvr2.h Tue Jan 23 11:19:32 2007 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: pvr2.h,v 1.24 2007-01-22 11:45:37 nkeynes Exp $1.6 + * $Id: pvr2.h,v 1.25 2007-01-23 11:19:32 nkeynes Exp $1.7 *1.8 * PVR2 (video chip) functions and macros.1.9 *1.10 @@ -132,6 +132,15 @@1.11 * Read a twiddled image from interleaved memory address space (aka 64-bit address1.12 * space), writing the image to the destination buffer in detwiddled format.1.13 * Width and height must be powers of 21.14 + * This version reads 4-bit pixels.1.15 + */1.16 +void pvr2_vram64_read_twiddled_4( char *dest, sh4addr_t src, uint32_t width, uint32_t height );1.17 +1.18 +1.19 +/**1.20 + * Read a twiddled image from interleaved memory address space (aka 64-bit address1.21 + * space), writing the image to the destination buffer in detwiddled format.1.22 + * Width and height must be powers of 21.23 * This version reads 8-bit pixels.1.24 */1.25 void pvr2_vram64_read_twiddled_8( char *dest, sh4addr_t src, uint32_t width, uint32_t height );1.26 @@ -151,14 +160,55 @@1.27 */1.28 void pvr2_vram64_read_stride( char *dest, uint32_t dest_line_bytes, sh4addr_t srcaddr,1.29 uint32_t src_line_bytes, uint32_t line_count );1.30 -1.31 -1.32 /**1.33 * Dump a portion of vram to a stream from the interleaved memory address1.34 * space.1.35 */1.36 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f );1.38 +1.39 +/**1.40 + * Describes a rendering buffer that's actually held in GL, for when we need1.41 + * to fetch the bits back to vram.1.42 + */1.43 +typedef struct pvr2_render_buffer {1.44 + sh4addr_t render_addr; /* The actual address rendered to in pvr ram */1.45 + uint32_t size; /* Length of rendering region in bytes */1.46 + int width, height;1.47 + int colour_format;1.48 +} *pvr2_render_buffer_t;1.49 +1.50 +/**1.51 + * Flush the indicated render buffer back to PVR. Caller is responsible for1.52 + * tracking whether there is actually anything in the buffer.1.53 + *1.54 + * @param buffer A render buffer indicating the address to store to, and the1.55 + * format the data needs to be in.1.56 + * @param backBuffer TRUE to flush the back buffer, FALSE for1.57 + * the front buffer.1.58 + */1.59 +void pvr2_render_buffer_copy_to_sh4( pvr2_render_buffer_t buffer,1.60 + gboolean backBuffer );1.61 +1.62 +/**1.63 + * Copy data from PVR ram into the GL render buffer.1.64 + *1.65 + * @param buffer A render buffer indicating the address to read from, and the1.66 + * format the data is in.1.67 + * @param backBuffer TRUE to write the back buffer, FALSE for1.68 + * the front buffer.1.69 + */1.70 +void pvr2_render_buffer_copy_from_sh4( pvr2_render_buffer_t buffer,1.71 + gboolean backBuffer );1.72 +1.73 +1.74 +/**1.75 + * Invalidate any caching on the supplied SH4 address1.76 + */1.77 +gboolean pvr2_render_buffer_invalidate( sh4addr_t addr );1.78 +1.79 +1.80 +1.81 /**************************** Tile Accelerator ***************************/1.82 /**1.83 * Process the data in the supplied buffer as an array of TA command lists.1.84 @@ -197,11 +247,6 @@1.85 gboolean pvr2_render_init( void );1.87 /**1.88 - * Invalidate any caching on the supplied SH4 address1.89 - */1.90 -gboolean pvr2_render_invalidate( sh4addr_t addr );1.91 -1.92 -/**1.93 * Render the current scene stored in PVR ram to the GL back buffer.1.94 */1.95 void pvr2_render_scene( void );
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