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lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 380:2e8166bf6832
prev377:fa18743f6905
next381:aade6c9aca4d
author nkeynes
date Wed Sep 12 11:31:16 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix load_spreg/store_spreg
Fix PREF
Add jump target debug checking
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.in Wed Sep 12 09:17:52 2007 +0000
1.2 +++ b/src/sh4/sh4x86.in Wed Sep 12 11:31:16 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4x86.in,v 1.6 2007-09-12 09:17:24 nkeynes Exp $
1.6 + * $Id: sh4x86.in,v 1.7 2007-09-12 11:31:16 nkeynes Exp $
1.7 *
1.8 * SH4 => x86 translation. This version does no real optimization, it just
1.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
1.10 @@ -20,6 +20,10 @@
1.11
1.12 #include <assert.h>
1.13
1.14 +#ifndef NDEBUG
1.15 +#define DEBUG_JUMPS 1
1.16 +#endif
1.17 +
1.18 #include "sh4/sh4core.h"
1.19 #include "sh4/sh4trans.h"
1.20 #include "sh4/x86op.h"
1.21 @@ -77,15 +81,6 @@
1.22 }
1.23 }
1.24
1.25 -#ifndef NDEBUG
1.26 -#define MARK_JMP(x,n) uint8_t *_mark_jmp_##x = xlat_output + n
1.27 -#define CHECK_JMP(x) assert( _mark_jmp_##x == xlat_output )
1.28 -#else
1.29 -#define MARK_JMP(x,n)
1.30 -#define CHECK_JMP(x)
1.31 -#endif
1.32 -
1.33 -
1.34 /**
1.35 * Emit an instruction to load an SH4 reg into a real register
1.36 */
1.37 @@ -112,14 +107,8 @@
1.38
1.39 }
1.40
1.41 -static inline void load_spreg( int x86reg, int regoffset )
1.42 -{
1.43 - /* mov [bp+n], reg */
1.44 - OP(0x8B);
1.45 - OP(0x45 + (x86reg<<3));
1.46 - OP(regoffset);
1.47 -}
1.48 -
1.49 +#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
1.50 +#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
1.51 /**
1.52 * Emit an instruction to load an immediate value into a register
1.53 */
1.54 @@ -138,13 +127,6 @@
1.55 OP(0x45 + (x86reg<<3));
1.56 OP(REG_OFFSET(r[sh4reg]));
1.57 }
1.58 -void static inline store_spreg( int x86reg, int regoffset ) {
1.59 - /* mov reg, [bp+n] */
1.60 - OP(0x89);
1.61 - OP(0x45 + (x86reg<<3));
1.62 - OP(regoffset);
1.63 -}
1.64 -
1.65
1.66 #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
1.67
1.68 @@ -368,6 +350,7 @@
1.69 load_imm32( R_EBP, (uint32_t)&sh4r );
1.70 PUSH_r32(R_EDI);
1.71 PUSH_r32(R_ESI);
1.72 + XOR_r32_r32(R_ESI, R_ESI);
1.73
1.74 sh4_x86.in_delay_slot = FALSE;
1.75 sh4_x86.priv_checked = FALSE;
1.76 @@ -404,17 +387,22 @@
1.77 uint8_t *end_ptr = xlat_output;
1.78 // Exception termination. Jump block for various exception codes:
1.79 PUSH_imm32( EXC_DATA_ADDR_READ );
1.80 - JMP_rel8( 33 );
1.81 + JMP_rel8( 33, target1 );
1.82 PUSH_imm32( EXC_DATA_ADDR_WRITE );
1.83 - JMP_rel8( 26 );
1.84 + JMP_rel8( 26, target2 );
1.85 PUSH_imm32( EXC_ILLEGAL );
1.86 - JMP_rel8( 19 );
1.87 + JMP_rel8( 19, target3 );
1.88 PUSH_imm32( EXC_SLOT_ILLEGAL );
1.89 - JMP_rel8( 12 );
1.90 + JMP_rel8( 12, target4 );
1.91 PUSH_imm32( EXC_FPU_DISABLED );
1.92 - JMP_rel8( 5 );
1.93 + JMP_rel8( 5, target5 );
1.94 PUSH_imm32( EXC_SLOT_FPU_DISABLED );
1.95 // target
1.96 + JMP_TARGET(target1);
1.97 + JMP_TARGET(target2);
1.98 + JMP_TARGET(target3);
1.99 + JMP_TARGET(target4);
1.100 + JMP_TARGET(target5);
1.101 load_spreg( R_ECX, REG_OFFSET(pc) );
1.102 ADD_r32_r32( R_ESI, R_ECX );
1.103 ADD_r32_r32( R_ESI, R_ECX );
1.104 @@ -542,13 +530,16 @@
1.105 load_reg( R_ECX, Rn );
1.106 XOR_r32_r32( R_ECX, R_EAX );
1.107 TEST_r8_r8( R_AL, R_AL );
1.108 - JE_rel8(13);
1.109 + JE_rel8(13, target1);
1.110 TEST_r8_r8( R_AH, R_AH ); // 2
1.111 - JE_rel8(9);
1.112 + JE_rel8(9, target2);
1.113 SHR_imm8_r32( 16, R_EAX ); // 3
1.114 TEST_r8_r8( R_AL, R_AL ); // 2
1.115 - JE_rel8(2);
1.116 + JE_rel8(2, target3);
1.117 TEST_r8_r8( R_AH, R_AH ); // 2
1.118 + JMP_TARGET(target1);
1.119 + JMP_TARGET(target2);
1.120 + JMP_TARGET(target3);
1.121 SETE_t();
1.122 :}
1.123 DIV0S Rm, Rn {:
1.124 @@ -574,10 +565,12 @@
1.125 SETC_r32( R_EDX ); // Q
1.126 load_spreg( R_EAX, R_Q );
1.127 CMP_sh4r_r32( R_M, R_EAX );
1.128 - JE_rel8(8);
1.129 + JE_rel8(8,mqequal);
1.130 ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
1.131 - JMP_rel8(3);
1.132 + JMP_rel8(3, mqnotequal);
1.133 + JMP_TARGET(mqequal);
1.134 SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
1.135 + JMP_TARGET(mqnotequal);
1.136 // TODO
1.137 :}
1.138 DMULS.L Rm, Rn {:
1.139 @@ -712,16 +705,16 @@
1.140 load_reg( R_EAX, Rn );
1.141 load_reg( R_ECX, Rm );
1.142 CMP_imm32_r32( 0, R_ECX );
1.143 - JAE_rel8(9);
1.144 + JAE_rel8(9, doshl);
1.145
1.146 NEG_r32( R_ECX ); // 2
1.147 AND_imm8_r8( 0x1F, R_CL ); // 3
1.148 SAR_r32_CL( R_EAX ); // 2
1.149 - JMP_rel8(5); // 2
1.150 -
1.151 + JMP_rel8(5, end); // 2
1.152 + JMP_TARGET(doshl);
1.153 AND_imm8_r8( 0x1F, R_CL ); // 3
1.154 SHL_r32_CL( R_EAX ); // 2
1.155 -
1.156 + JMP_TARGET(end);
1.157 store_reg( R_EAX, Rn );
1.158 :}
1.159 SHLD Rm, Rn {:
1.160 @@ -1131,8 +1124,9 @@
1.161 } else {
1.162 load_imm32( R_EDI, pc + 2 );
1.163 CMP_imm8s_sh4r( 0, R_T );
1.164 - JNE_rel8( 5 );
1.165 + JNE_rel8( 5, nottaken );
1.166 load_imm32( R_EDI, disp + pc + 4 );
1.167 + JMP_TARGET(nottaken);
1.168 INC_r32(R_ESI);
1.169 return 1;
1.170 }
1.171 @@ -1143,8 +1137,9 @@
1.172 } else {
1.173 load_imm32( R_EDI, pc + 2 );
1.174 CMP_imm8s_sh4r( 0, R_T );
1.175 - JNE_rel8( 5 );
1.176 + JNE_rel8( 5, nottaken );
1.177 load_imm32( R_EDI, disp + pc + 4 );
1.178 + JMP_TARGET(nottaken);
1.179 sh4_x86.in_delay_slot = TRUE;
1.180 INC_r32(R_ESI);
1.181 return 0;
1.182 @@ -1201,8 +1196,9 @@
1.183 } else {
1.184 load_imm32( R_EDI, pc + 2 );
1.185 CMP_imm8s_sh4r( 0, R_T );
1.186 - JE_rel8( 5 );
1.187 + JE_rel8( 5, nottaken );
1.188 load_imm32( R_EDI, disp + pc + 4 );
1.189 + JMP_TARGET(nottaken);
1.190 INC_r32(R_ESI);
1.191 return 1;
1.192 }
1.193 @@ -1213,8 +1209,9 @@
1.194 } else {
1.195 load_imm32( R_EDI, pc + 2 );
1.196 CMP_imm8s_sh4r( 0, R_T );
1.197 - JE_rel8( 5 );
1.198 + JE_rel8( 5, nottaken );
1.199 load_imm32( R_EDI, disp + pc + 4 );
1.200 + JMP_TARGET(nottaken);
1.201 sh4_x86.in_delay_slot = TRUE;
1.202 INC_r32(R_ESI);
1.203 return 0;
1.204 @@ -1319,11 +1316,12 @@
1.205 load_spreg( R_ECX, R_FPSCR );
1.206 load_fr_bank( R_EDX );
1.207 TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.208 - JNE_rel8(8);
1.209 + JNE_rel8(8, doublesize);
1.210 load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
1.211 store_fr( R_EDX, R_EAX, FRn );
1.212 if( FRm&1 ) {
1.213 - JMP_rel8(22);
1.214 + JMP_rel8(22, end);
1.215 + JMP_TARGET(doublesize);
1.216 load_xf_bank( R_ECX );
1.217 load_fr( R_ECX, R_EAX, FRm-1 );
1.218 if( FRn&1 ) {
1.219 @@ -1335,20 +1333,23 @@
1.220 store_fr( R_EDX, R_EAX, FRn-1 );
1.221 store_fr( R_EDX, R_ECX, FRn );
1.222 }
1.223 + JMP_TARGET(end);
1.224 } else /* FRm&1 == 0 */ {
1.225 if( FRn&1 ) {
1.226 - JMP_rel8(22);
1.227 + JMP_rel8(22, end);
1.228 load_xf_bank( R_ECX );
1.229 load_fr( R_EDX, R_EAX, FRm );
1.230 load_fr( R_EDX, R_EDX, FRm+1 );
1.231 store_fr( R_ECX, R_EAX, FRn-1 );
1.232 store_fr( R_ECX, R_EDX, FRn );
1.233 + JMP_TARGET(end);
1.234 } else /* FRn&1 == 0 */ {
1.235 - JMP_rel8(12);
1.236 + JMP_rel8(12, end);
1.237 load_fr( R_EDX, R_EAX, FRm );
1.238 load_fr( R_EDX, R_ECX, FRm+1 );
1.239 store_fr( R_EDX, R_EAX, FRn );
1.240 store_fr( R_EDX, R_ECX, FRn+1 );
1.241 + JMP_TARGET(end);
1.242 }
1.243 }
1.244 :}
1.245 @@ -1358,20 +1359,27 @@
1.246 check_walign32( R_EDX );
1.247 load_spreg( R_ECX, R_FPSCR );
1.248 TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.249 - JNE_rel8(20);
1.250 + JNE_rel8(20, doublesize);
1.251 load_fr_bank( R_ECX );
1.252 load_fr( R_ECX, R_EAX, FRm );
1.253 MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
1.254 if( FRm&1 ) {
1.255 - JMP_rel8( 46 );
1.256 + JMP_rel8( 46, end );
1.257 + JMP_TARGET(doublesize);
1.258 load_xf_bank( R_ECX );
1.259 + load_fr( R_ECX, R_EAX, FRm&0x0E );
1.260 + load_fr( R_ECX, R_ECX, FRm|0x01 );
1.261 + MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.262 + JMP_TARGET(end);
1.263 } else {
1.264 - JMP_rel8( 39 );
1.265 + JMP_rel8( 39, end );
1.266 + JMP_TARGET(doublesize);
1.267 load_fr_bank( R_ECX );
1.268 + load_fr( R_ECX, R_EAX, FRm&0x0E );
1.269 + load_fr( R_ECX, R_ECX, FRm|0x01 );
1.270 + MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.271 + JMP_TARGET(end);
1.272 }
1.273 - load_fr( R_ECX, R_EAX, FRm&0x0E );
1.274 - load_fr( R_ECX, R_ECX, FRm|0x01 );
1.275 - MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.276 :}
1.277 FMOV @Rm, FRn {:
1.278 check_fpuen();
1.279 @@ -1379,22 +1387,28 @@
1.280 check_ralign32( R_EDX );
1.281 load_spreg( R_ECX, R_FPSCR );
1.282 TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.283 - JNE_rel8(19);
1.284 + JNE_rel8(19, doublesize);
1.285 MEM_READ_LONG( R_EDX, R_EAX );
1.286 load_fr_bank( R_ECX );
1.287 store_fr( R_ECX, R_EAX, FRn );
1.288 if( FRn&1 ) {
1.289 - JMP_rel8(46);
1.290 + JMP_rel8(46, end);
1.291 + JMP_TARGET(doublesize);
1.292 MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
1.293 load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
1.294 load_xf_bank( R_ECX );
1.295 + store_fr( R_ECX, R_EAX, FRn&0x0E );
1.296 + store_fr( R_ECX, R_EDX, FRn|0x01 );
1.297 + JMP_TARGET(end);
1.298 } else {
1.299 - JMP_rel8(36);
1.300 + JMP_rel8(36, end);
1.301 + JMP_TARGET(doublesize);
1.302 MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
1.303 load_fr_bank( R_ECX );
1.304 + store_fr( R_ECX, R_EAX, FRn&0x0E );
1.305 + store_fr( R_ECX, R_EDX, FRn|0x01 );
1.306 + JMP_TARGET(end);
1.307 }
1.308 - store_fr( R_ECX, R_EAX, FRn&0x0E );
1.309 - store_fr( R_ECX, R_EDX, FRn|0x01 );
1.310 :}
1.311 FMOV FRm, @-Rn {:
1.312 check_fpuen();
1.313 @@ -1402,24 +1416,33 @@
1.314 check_walign32( R_EDX );
1.315 load_spreg( R_ECX, R_FPSCR );
1.316 TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.317 - JNE_rel8(20);
1.318 + JNE_rel8(20, doublesize);
1.319 load_fr_bank( R_ECX );
1.320 load_fr( R_ECX, R_EAX, FRm );
1.321 ADD_imm8s_r32(-4,R_EDX);
1.322 store_reg( R_EDX, Rn );
1.323 MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
1.324 if( FRm&1 ) {
1.325 - JMP_rel8( 46 );
1.326 + JMP_rel8( 46, end );
1.327 + JMP_TARGET(doublesize);
1.328 load_xf_bank( R_ECX );
1.329 + load_fr( R_ECX, R_EAX, FRm&0x0E );
1.330 + load_fr( R_ECX, R_ECX, FRm|0x01 );
1.331 + ADD_imm8s_r32(-8,R_EDX);
1.332 + store_reg( R_EDX, Rn );
1.333 + MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.334 + JMP_TARGET(end);
1.335 } else {
1.336 - JMP_rel8( 39 );
1.337 + JMP_rel8( 39, end );
1.338 + JMP_TARGET(doublesize);
1.339 load_fr_bank( R_ECX );
1.340 + load_fr( R_ECX, R_EAX, FRm&0x0E );
1.341 + load_fr( R_ECX, R_ECX, FRm|0x01 );
1.342 + ADD_imm8s_r32(-8,R_EDX);
1.343 + store_reg( R_EDX, Rn );
1.344 + MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.345 + JMP_TARGET(end);
1.346 }
1.347 - load_fr( R_ECX, R_EAX, FRm&0x0E );
1.348 - load_fr( R_ECX, R_ECX, FRm|0x01 );
1.349 - ADD_imm8s_r32(-8,R_EDX);
1.350 - store_reg( R_EDX, Rn );
1.351 - MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.352 :}
1.353 FMOV @Rm+, FRn {:
1.354 check_fpuen();
1.355 @@ -1428,28 +1451,33 @@
1.356 MOV_r32_r32( R_EDX, R_EAX );
1.357 load_spreg( R_ECX, R_FPSCR );
1.358 TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.359 - JNE_rel8(25);
1.360 + JNE_rel8(25, doublesize);
1.361 ADD_imm8s_r32( 4, R_EAX );
1.362 store_reg( R_EAX, Rm );
1.363 MEM_READ_LONG( R_EDX, R_EAX );
1.364 load_fr_bank( R_ECX );
1.365 store_fr( R_ECX, R_EAX, FRn );
1.366 if( FRn&1 ) {
1.367 - JMP_rel8(52);
1.368 + JMP_rel8(52, end);
1.369 + JMP_TARGET(doublesize);
1.370 ADD_imm8s_r32( 8, R_EAX );
1.371 store_reg(R_EAX, Rm);
1.372 MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
1.373 load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
1.374 load_xf_bank( R_ECX );
1.375 + store_fr( R_ECX, R_EAX, FRn&0x0E );
1.376 + store_fr( R_ECX, R_EDX, FRn|0x01 );
1.377 + JMP_TARGET(end);
1.378 } else {
1.379 - JMP_rel8(42);
1.380 + JMP_rel8(42, end);
1.381 ADD_imm8s_r32( 8, R_EAX );
1.382 store_reg(R_EAX, Rm);
1.383 MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
1.384 load_fr_bank( R_ECX );
1.385 + store_fr( R_ECX, R_EAX, FRn&0x0E );
1.386 + store_fr( R_ECX, R_EDX, FRn|0x01 );
1.387 + JMP_TARGET(end);
1.388 }
1.389 - store_fr( R_ECX, R_EAX, FRn&0x0E );
1.390 - store_fr( R_ECX, R_EDX, FRn|0x01 );
1.391 :}
1.392 FMOV FRm, @(R0, Rn) {:
1.393 check_fpuen();
1.394 @@ -1458,20 +1486,27 @@
1.395 check_walign32( R_EDX );
1.396 load_spreg( R_ECX, R_FPSCR );
1.397 TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.398 - JNE_rel8(20);
1.399 + JNE_rel8(20, doublesize);
1.400 load_fr_bank( R_ECX );
1.401 load_fr( R_ECX, R_EAX, FRm );
1.402 MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
1.403 if( FRm&1 ) {
1.404 - JMP_rel8( 46 );
1.405 + JMP_rel8( 46, end );
1.406 + JMP_TARGET(doublesize);
1.407 load_xf_bank( R_ECX );
1.408 + load_fr( R_ECX, R_EAX, FRm&0x0E );
1.409 + load_fr( R_ECX, R_ECX, FRm|0x01 );
1.410 + MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.411 + JMP_TARGET(end);
1.412 } else {
1.413 - JMP_rel8( 39 );
1.414 + JMP_rel8( 39, end );
1.415 + JMP_TARGET(doublesize);
1.416 load_fr_bank( R_ECX );
1.417 + load_fr( R_ECX, R_EAX, FRm&0x0E );
1.418 + load_fr( R_ECX, R_ECX, FRm|0x01 );
1.419 + MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.420 + JMP_TARGET(end);
1.421 }
1.422 - load_fr( R_ECX, R_EAX, FRm&0x0E );
1.423 - load_fr( R_ECX, R_ECX, FRm|0x01 );
1.424 - MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
1.425 :}
1.426 FMOV @(R0, Rm), FRn {:
1.427 check_fpuen();
1.428 @@ -1480,40 +1515,48 @@
1.429 check_ralign32( R_EDX );
1.430 load_spreg( R_ECX, R_FPSCR );
1.431 TEST_imm32_r32( FPSCR_SZ, R_ECX );
1.432 - JNE_rel8(19);
1.433 + JNE_rel8(19, doublesize);
1.434 MEM_READ_LONG( R_EDX, R_EAX );
1.435 load_fr_bank( R_ECX );
1.436 store_fr( R_ECX, R_EAX, FRn );
1.437 if( FRn&1 ) {
1.438 - JMP_rel8(46);
1.439 + JMP_rel8(46, end);
1.440 + JMP_TARGET(doublesize);
1.441 MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
1.442 load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
1.443 load_xf_bank( R_ECX );
1.444 + store_fr( R_ECX, R_EAX, FRn&0x0E );
1.445 + store_fr( R_ECX, R_EDX, FRn|0x01 );
1.446 + JMP_TARGET(end);
1.447 } else {
1.448 - JMP_rel8(36);
1.449 + JMP_rel8(36, end);
1.450 + JMP_TARGET(doublesize);
1.451 MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
1.452 load_fr_bank( R_ECX );
1.453 + store_fr( R_ECX, R_EAX, FRn&0x0E );
1.454 + store_fr( R_ECX, R_EDX, FRn|0x01 );
1.455 + JMP_TARGET(end);
1.456 }
1.457 - store_fr( R_ECX, R_EAX, FRn&0x0E );
1.458 - store_fr( R_ECX, R_EDX, FRn|0x01 );
1.459 :}
1.460 FLDI0 FRn {: /* IFF PR=0 */
1.461 check_fpuen();
1.462 load_spreg( R_ECX, R_FPSCR );
1.463 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.464 - JNE_rel8(8);
1.465 + JNE_rel8(8, end);
1.466 XOR_r32_r32( R_EAX, R_EAX );
1.467 load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.468 store_fr( R_ECX, R_EAX, FRn );
1.469 + JMP_TARGET(end);
1.470 :}
1.471 FLDI1 FRn {: /* IFF PR=0 */
1.472 check_fpuen();
1.473 load_spreg( R_ECX, R_FPSCR );
1.474 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.475 - JNE_rel8(11);
1.476 + JNE_rel8(11, end);
1.477 load_imm32(R_EAX, 0x3F800000);
1.478 load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.479 store_fr( R_ECX, R_EAX, FRn );
1.480 + JMP_TARGET(end);
1.481 :}
1.482
1.483 FLOAT FPUL, FRn {:
1.484 @@ -1522,10 +1565,12 @@
1.485 load_spreg(R_EDX, REG_OFFSET(fr_bank));
1.486 FILD_sh4r(R_FPUL);
1.487 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.488 - JNE_rel8(5);
1.489 + JNE_rel8(5, doubleprec);
1.490 pop_fr( R_EDX, FRn );
1.491 - JMP_rel8(3);
1.492 + JMP_rel8(3, end);
1.493 + JMP_TARGET(doubleprec);
1.494 pop_dr( R_EDX, FRn );
1.495 + JMP_TARGET(end);
1.496 :}
1.497 FTRC FRm, FPUL {:
1.498 check_fpuen();
1.499 @@ -1547,20 +1592,22 @@
1.500 check_fpuen();
1.501 load_spreg( R_ECX, R_FPSCR );
1.502 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.503 - JE_rel8(9); // only when PR=1
1.504 + JE_rel8(9, end); // only when PR=1
1.505 load_fr_bank( R_ECX );
1.506 push_dr( R_ECX, FRm );
1.507 pop_fpul();
1.508 + JMP_TARGET(end);
1.509 :}
1.510 FCNVSD FPUL, FRn {:
1.511 check_fpuen();
1.512 check_fpuen();
1.513 load_spreg( R_ECX, R_FPSCR );
1.514 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.515 - JE_rel8(9); // only when PR=1
1.516 + JE_rel8(9, end); // only when PR=1
1.517 load_fr_bank( R_ECX );
1.518 push_fpul();
1.519 pop_dr( R_ECX, FRn );
1.520 + JMP_TARGET(end);
1.521 :}
1.522
1.523 /* Floating point instructions */
1.524 @@ -1569,66 +1616,74 @@
1.525 load_spreg( R_ECX, R_FPSCR );
1.526 load_fr_bank( R_EDX );
1.527 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.528 - JNE_rel8(10);
1.529 + JNE_rel8(10, doubleprec);
1.530 push_fr(R_EDX, FRn); // 3
1.531 FABS_st0(); // 2
1.532 pop_fr( R_EDX, FRn); //3
1.533 - JMP_rel8(8); // 2
1.534 + JMP_rel8(8,end); // 2
1.535 + JMP_TARGET(doubleprec);
1.536 push_dr(R_EDX, FRn);
1.537 FABS_st0();
1.538 pop_dr(R_EDX, FRn);
1.539 + JMP_TARGET(end);
1.540 :}
1.541 FADD FRm, FRn {:
1.542 check_fpuen();
1.543 load_spreg( R_ECX, R_FPSCR );
1.544 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.545 load_fr_bank( R_EDX );
1.546 - JNE_rel8(13);
1.547 + JNE_rel8(13,doubleprec);
1.548 push_fr(R_EDX, FRm);
1.549 push_fr(R_EDX, FRn);
1.550 FADDP_st(1);
1.551 pop_fr(R_EDX, FRn);
1.552 - JMP_rel8(11);
1.553 + JMP_rel8(11,end);
1.554 + JMP_TARGET(doubleprec);
1.555 push_dr(R_EDX, FRm);
1.556 push_dr(R_EDX, FRn);
1.557 FADDP_st(1);
1.558 pop_dr(R_EDX, FRn);
1.559 + JMP_TARGET(end);
1.560 :}
1.561 FDIV FRm, FRn {:
1.562 check_fpuen();
1.563 load_spreg( R_ECX, R_FPSCR );
1.564 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.565 load_fr_bank( R_EDX );
1.566 - JNE_rel8(13);
1.567 + JNE_rel8(13, doubleprec);
1.568 push_fr(R_EDX, FRn);
1.569 push_fr(R_EDX, FRm);
1.570 FDIVP_st(1);
1.571 pop_fr(R_EDX, FRn);
1.572 - JMP_rel8(11);
1.573 + JMP_rel8(11, end);
1.574 + JMP_TARGET(doubleprec);
1.575 push_dr(R_EDX, FRn);
1.576 push_dr(R_EDX, FRm);
1.577 FDIVP_st(1);
1.578 pop_dr(R_EDX, FRn);
1.579 + JMP_TARGET(end);
1.580 :}
1.581 FMAC FR0, FRm, FRn {:
1.582 check_fpuen();
1.583 load_spreg( R_ECX, R_FPSCR );
1.584 load_spreg( R_EDX, REG_OFFSET(fr_bank));
1.585 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.586 - JNE_rel8(18);
1.587 + JNE_rel8(18, doubleprec);
1.588 push_fr( R_EDX, 0 );
1.589 push_fr( R_EDX, FRm );
1.590 FMULP_st(1);
1.591 push_fr( R_EDX, FRn );
1.592 FADDP_st(1);
1.593 pop_fr( R_EDX, FRn );
1.594 - JMP_rel8(16);
1.595 + JMP_rel8(16, end);
1.596 + JMP_TARGET(doubleprec);
1.597 push_dr( R_EDX, 0 );
1.598 push_dr( R_EDX, FRm );
1.599 FMULP_st(1);
1.600 push_dr( R_EDX, FRn );
1.601 FADDP_st(1);
1.602 pop_dr( R_EDX, FRn );
1.603 + JMP_TARGET(end);
1.604 :}
1.605
1.606 FMUL FRm, FRn {:
1.607 @@ -1636,72 +1691,81 @@
1.608 load_spreg( R_ECX, R_FPSCR );
1.609 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.610 load_fr_bank( R_EDX );
1.611 - JNE_rel8(13);
1.612 + JNE_rel8(13, doubleprec);
1.613 push_fr(R_EDX, FRm);
1.614 push_fr(R_EDX, FRn);
1.615 FMULP_st(1);
1.616 pop_fr(R_EDX, FRn);
1.617 - JMP_rel8(11);
1.618 + JMP_rel8(11, end);
1.619 + JMP_TARGET(doubleprec);
1.620 push_dr(R_EDX, FRm);
1.621 push_dr(R_EDX, FRn);
1.622 FMULP_st(1);
1.623 pop_dr(R_EDX, FRn);
1.624 + JMP_TARGET(end);
1.625 :}
1.626 FNEG FRn {:
1.627 check_fpuen();
1.628 load_spreg( R_ECX, R_FPSCR );
1.629 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.630 load_fr_bank( R_EDX );
1.631 - JNE_rel8(10);
1.632 + JNE_rel8(10, doubleprec);
1.633 push_fr(R_EDX, FRn);
1.634 FCHS_st0();
1.635 pop_fr(R_EDX, FRn);
1.636 - JMP_rel8(8);
1.637 + JMP_rel8(8, end);
1.638 + JMP_TARGET(doubleprec);
1.639 push_dr(R_EDX, FRn);
1.640 FCHS_st0();
1.641 pop_dr(R_EDX, FRn);
1.642 + JMP_TARGET(end);
1.643 :}
1.644 FSRRA FRn {:
1.645 check_fpuen();
1.646 load_spreg( R_ECX, R_FPSCR );
1.647 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.648 load_fr_bank( R_EDX );
1.649 - JNE_rel8(12); // PR=0 only
1.650 + JNE_rel8(12, end); // PR=0 only
1.651 FLD1_st0();
1.652 push_fr(R_EDX, FRn);
1.653 FSQRT_st0();
1.654 FDIVP_st(1);
1.655 pop_fr(R_EDX, FRn);
1.656 + JMP_TARGET(end);
1.657 :}
1.658 FSQRT FRn {:
1.659 check_fpuen();
1.660 load_spreg( R_ECX, R_FPSCR );
1.661 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.662 load_fr_bank( R_EDX );
1.663 - JNE_rel8(10);
1.664 + JNE_rel8(10, doubleprec);
1.665 push_fr(R_EDX, FRn);
1.666 FSQRT_st0();
1.667 pop_fr(R_EDX, FRn);
1.668 - JMP_rel8(8);
1.669 + JMP_rel8(8, end);
1.670 + JMP_TARGET(doubleprec);
1.671 push_dr(R_EDX, FRn);
1.672 FSQRT_st0();
1.673 pop_dr(R_EDX, FRn);
1.674 + JMP_TARGET(end);
1.675 :}
1.676 FSUB FRm, FRn {:
1.677 check_fpuen();
1.678 load_spreg( R_ECX, R_FPSCR );
1.679 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.680 load_fr_bank( R_EDX );
1.681 - JNE_rel8(13);
1.682 + JNE_rel8(13, doubleprec);
1.683 push_fr(R_EDX, FRn);
1.684 push_fr(R_EDX, FRm);
1.685 FMULP_st(1);
1.686 pop_fr(R_EDX, FRn);
1.687 - JMP_rel8(11);
1.688 + JMP_rel8(11, end);
1.689 + JMP_TARGET(doubleprec);
1.690 push_dr(R_EDX, FRn);
1.691 push_dr(R_EDX, FRm);
1.692 FMULP_st(1);
1.693 pop_dr(R_EDX, FRn);
1.694 + JMP_TARGET(end);
1.695 :}
1.696
1.697 FCMP/EQ FRm, FRn {:
1.698 @@ -1709,27 +1773,31 @@
1.699 load_spreg( R_ECX, R_FPSCR );
1.700 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.701 load_fr_bank( R_EDX );
1.702 - JNE_rel8(8);
1.703 + JNE_rel8(8, doubleprec);
1.704 push_fr(R_EDX, FRm);
1.705 push_fr(R_EDX, FRn);
1.706 - JMP_rel8(6);
1.707 + JMP_rel8(6, end);
1.708 + JMP_TARGET(doubleprec);
1.709 push_dr(R_EDX, FRm);
1.710 push_dr(R_EDX, FRn);
1.711 FCOMIP_st(1);
1.712 SETE_t();
1.713 FPOP_st();
1.714 + JMP_TARGET(end);
1.715 :}
1.716 FCMP/GT FRm, FRn {:
1.717 check_fpuen();
1.718 load_spreg( R_ECX, R_FPSCR );
1.719 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.720 load_fr_bank( R_EDX );
1.721 - JNE_rel8(8);
1.722 + JNE_rel8(8, doubleprec);
1.723 push_fr(R_EDX, FRm);
1.724 push_fr(R_EDX, FRn);
1.725 - JMP_rel8(6);
1.726 + JMP_rel8(6, end);
1.727 + JMP_TARGET(doubleprec);
1.728 push_dr(R_EDX, FRm);
1.729 push_dr(R_EDX, FRn);
1.730 + JMP_TARGET(end);
1.731 FCOMIP_st(1);
1.732 SETA_t();
1.733 FPOP_st();
1.734 @@ -1929,8 +1997,9 @@
1.735 PUSH_r32( R_EAX );
1.736 AND_imm32_r32( 0xFC000000, R_EAX );
1.737 CMP_imm32_r32( 0xE0000000, R_EAX );
1.738 - JNE_rel8(8);
1.739 + JNE_rel8(7, end);
1.740 call_func0( sh4_flush_store_queue );
1.741 + JMP_TARGET(end);
1.742 ADD_imm8s_r32( 4, R_ESP );
1.743 :}
1.744 SLEEP {: /* TODO */ :}
.