1.1 --- a/src/sh4/sh4x86.in	Thu Oct 30 05:50:21 2008 +0000
     1.2 +++ b/src/sh4/sh4x86.in	Fri Oct 31 02:57:59 2008 +0000
     1.3 @@ -411,16 +411,6 @@
     1.4      assert( IS_IN_ICACHE(pc) );
     1.5      ir = *(uint16_t *)GET_ICACHE_PTR(pc);
     1.6      
     1.7 -	/* PC is not in the current icache - this usually means we're running
     1.8 -	 * with MMU on, and we've gone past the end of the page. And since 
     1.9 -	 * sh4_translate_block is pretty careful about this, it means we're
    1.10 -	 * almost certainly in a delay slot.
    1.11 -	 *
    1.12 -	 * Since we can't assume the page is present (and we can't fault it in
    1.13 -	 * at this point, inline a call to sh4_execute_instruction (with a few
    1.14 -	 * small repairs to cope with the different environment).
    1.15 -	 */
    1.16 -
    1.17      if( !sh4_x86.in_delay_slot ) {
    1.18  	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
    1.19      }
    1.20 @@ -444,7 +434,7 @@
    1.21  ADDC Rm, Rn {:
    1.22      COUNT_INST(I_ADDC);
    1.23      if( sh4_x86.tstate != TSTATE_C ) {
    1.24 -	LDC_t();
    1.25 +        LDC_t();
    1.26      }
    1.27      load_reg( R_EAX, Rm );
    1.28      load_reg( R_ECX, Rn );
    1.29 @@ -2567,9 +2557,13 @@
    1.30      AND_imm32_r32( 0xFC000000, R_ECX );
    1.31      CMP_imm32_r32( 0xE0000000, R_ECX );
    1.32      JNE_rel8(end);
    1.33 -    call_func1( sh4_flush_store_queue, R_EAX );
    1.34 -    TEST_r32_r32( R_EAX, R_EAX );
    1.35 -    JE_exc(-1);
    1.36 +    if( sh4_x86.tlb_on ) {
    1.37 +    	call_func1( sh4_flush_store_queue_mmu, R_EAX );
    1.38 +        TEST_r32_r32( R_EAX, R_EAX );
    1.39 +        JE_exc(-1);
    1.40 +    } else {
    1.41 +    	call_func1( sh4_flush_store_queue, R_EAX );
    1.42 +   	}
    1.43      JMP_TARGET(end);
    1.44      sh4_x86.tstate = TSTATE_NONE;
    1.45  :}