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lxdream.org :: lxdream/test/sh4/tlb.s :: diff
lxdream 0.9.1
released Jun 29
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filename test/sh4/tlb.s
changeset 555:309c97260912
next1065:bc1cc0c54917
author nkeynes
date Tue Jan 01 04:32:01 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Add initial TLB tests
file annotate diff log raw
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/test/sh4/tlb.s Tue Jan 01 04:32:01 2008 +0000
1.3 @@ -0,0 +1,165 @@
1.4 +.section .text
1.5 +.include "sh4/inc.s"
1.6 +!
1.7 +! Test for correct UTLB operation.
1.8 +!
1.9 +! Note we don't test triggering a TLB multiple-hit exception - it's a reset
1.10 +! rather than a regular exception.
1.11 +
1.12 +.global _test_tlb
1.13 +_test_tlb:
1.14 + start_test
1.15 +
1.16 +! Turn on AT, and flush the current TLB (if any)
1.17 +! Initialize to SV=0, SQMD=0, URB=URC=LRUI=0
1.18 + mov.l test_tlb_mmucr, r0
1.19 + mov #5, r1
1.20 + mov.l r1, @r0
1.21 +
1.22 +! Privileged mode tests first (much easier)
1.23 + add #1, r12
1.24 + mov.l test_tlb1_pteh, r1
1.25 + mov.l test_tlb_pteh, r2
1.26 + mov.l r1, @r2
1.27 + mov.l test_tlb1_ptel, r1
1.28 + mov.l test_tlb_ptel, r2
1.29 + mov.l r1, @r2
1.30 + ldtlb
1.31 +
1.32 +! Simple read
1.33 + mov.l test_tlb1_direct, r3
1.34 + mov #42, r2
1.35 + mov.l r2, @r3
1.36 + mov.l test_tlb1_mmu, r0
1.37 + mov.l @r0, r1
1.38 + cmp/eq r1, r2
1.39 + bt test_tlb_2
1.40 + fail test_tlb_str_k
1.41 + bra test_tlb_2
1.42 + nop
1.43 +test_tlb1_pteh:
1.44 + .long 0x12345012
1.45 +test_tlb1_ptel:
1.46 + .long 0x005F8120
1.47 +
1.48 +test_tlb_2:
1.49 + ! Trigger an initial-page-write exception
1.50 + add #1, r12
1.51 + expect_exc 0x00000080
1.52 + mov.l test_tlb1_mmu, r0
1.53 +test_tlb2_exc:
1.54 + mov.l r0, @r0
1.55 + assert_tlb_exc_caught test_tlb_str_k test_tlb2_exc test_tlb1_mmu
1.56 +
1.57 +test_tlb_3:
1.58 + ! Trigger a missing page read exception by invalidation
1.59 + add #1, r12
1.60 + mov.l test_tlb3_addr, r1
1.61 + mov.l test_tlb3_data, r2
1.62 + mov.l r2, @r1
1.63 +
1.64 + expect_exc 0x00000040
1.65 + mov.l test_tlb1_mmu, r0
1.66 +test_tlb3_exc:
1.67 + mov.l @r0, r2
1.68 + assert_tlb_exc_caught test_tlb_str_k, test_tlb3_exc, test_tlb1_mmu
1.69 + bra test_tlb_4
1.70 + nop
1.71 +
1.72 +test_tlb3_addr:
1.73 + .long 0xF6000F80
1.74 +test_tlb3_data:
1.75 + .long 0x12345212
1.76 +
1.77 +test_tlb_4:
1.78 + ! Test missing page write exception on the same page
1.79 + add #1, r12
1.80 + expect_exc 0x00000060
1.81 + mov.l test_tlb1_mmu, r0
1.82 +test_tlb4_exc:
1.83 + mov.l r2, @r0
1.84 + assert_tlb_exc_caught test_tlb_str_k, test_tlb4_exc, test_tlb1_mmu
1.85 +
1.86 +test_tlb_5: ! Test initial write exception
1.87 + add #1, r12
1.88 +
1.89 + mov.l test_tlb5_addr, r1
1.90 + mov.l test_tlb5_data, r2
1.91 + mov.l r2, @r1
1.92 +
1.93 + expect_exc 0x00000080
1.94 + mov.l test_tlb1_mmu, r0
1.95 + mov #63, r3
1.96 +test_tlb5_exc:
1.97 + mov.l r3, @r0
1.98 + assert_tlb_exc_caught test_tlb_str_k, test_tlb5_exc, test_tlb1_mmu
1.99 + mov.l test_tlb1_direct, r3
1.100 + mov.l @r3, r4
1.101 + mov #42, r2
1.102 + cmp/eq r2, r4
1.103 + bf test_tlb5_fail
1.104 + mov.l test_tlb1_mmu, r0
1.105 + mov.l @r0, r3
1.106 + cmp/eq r2, r3
1.107 + bt test_tlb_6
1.108 +test_tlb5_fail:
1.109 + fail test_tlb_str_k
1.110 +
1.111 +test_tlb5_addr:
1.112 + .long 0xF6000F80
1.113 +test_tlb5_data:
1.114 + .long 0x12345112
1.115 +
1.116 +test_tlb_6:! Test successful write.
1.117 + add #1, r12
1.118 +
1.119 + mov.l test_tlb6_addr, r1
1.120 + mov.l test_tlb6_data, r2
1.121 + mov.l r2, @r1
1.122 +
1.123 + mov.l test_tlb1_mmu, r0
1.124 + mov #77, r3
1.125 + mov.l r3, @r0
1.126 + mov.l test_tlb1_direct, r1
1.127 + mov.l @r1, r2
1.128 + cmp/eq r2, r3
1.129 + bt test_tlb_7
1.130 + fail test_tlb_str_k
1.131 + bra test_tlb_7
1.132 + nop
1.133 +
1.134 +test_tlb_7:
1.135 + bra test_tlb_end
1.136 + nop
1.137 +
1.138 +test_tlb6_addr:
1.139 + .long 0xF6000F80
1.140 +test_tlb6_data:
1.141 + .long 0x12345312
1.142 +
1.143 +
1.144 +test_tlb1_mmu:
1.145 + .long 0x12345040
1.146 +test_tlb1_direct:
1.147 + .long 0xA05F8040 ! Display border colour
1.148 +
1.149 +test_tlb_end:
1.150 + xor r0, r0
1.151 + mov.l test_tlb_mmucr, r1
1.152 + mov.l r0, @r1
1.153 +
1.154 + end_test test_tlb_str_k
1.155 +
1.156 +test_tlb_mmucr:
1.157 + .long 0xFF000010
1.158 +test_tlb_pteh:
1.159 + .long 0xFF000000
1.160 +test_tlb_ptel:
1.161 + .long 0xFF000004
1.162 +test_tlb_tea:
1.163 + .long 0xFF00000C
1.164 +test_tlb_str:
1.165 + .string "TLB"
1.166 +.align 4
1.167 +test_tlb_str_k:
1.168 + .long test_tlb_str
.