Search
lxdream.org :: lxdream/src/asic.c :: diff
lxdream 0.9.1
released Jun 29
Download Now
filename src/asic.c
changeset 56:3224dceaf2a3
prev42:d06affd949ec
next94:8d80d9c7cc7d
author nkeynes
date Sun Jan 01 08:09:42 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Implement PVR DMA channel
file annotate diff log raw
1.1 --- a/src/asic.c Mon Dec 26 10:48:55 2005 +0000
1.2 +++ b/src/asic.c Sun Jan 01 08:09:42 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: asic.c,v 1.9 2005-12-26 10:48:55 nkeynes Exp $
1.6 + * $Id: asic.c,v 1.10 2006-01-01 08:09:42 nkeynes Exp $
1.7 *
1.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
1.9 * and DMA).
1.10 @@ -23,6 +23,7 @@
1.11 #include "dream.h"
1.12 #include "mem.h"
1.13 #include "sh4/intc.h"
1.14 +#include "sh4/dmac.h"
1.15 #include "dreamcast.h"
1.16 #include "maple/maple.h"
1.17 #include "gdrom/ide.h"
1.18 @@ -55,27 +56,40 @@
1.19 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
1.20 {
1.21 switch( reg ) {
1.22 - case PIRQ0:
1.23 - case PIRQ1:
1.24 - case PIRQ2:
1.25 - /* Clear any interrupts */
1.26 - MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
1.27 - asic_check_cleared_events();
1.28 - break;
1.29 - case MAPLE_STATE:
1.30 - MMIO_WRITE( ASIC, reg, val );
1.31 - if( val & 1 ) {
1.32 - uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
1.33 - WARN( "Maple request initiated at %08X, halting", maple_addr );
1.34 - maple_handle_buffer( maple_addr );
1.35 - MMIO_WRITE( ASIC, reg, 0 );
1.36 -// dreamcast_stop();
1.37 - }
1.38 - break;
1.39 - default:
1.40 - MMIO_WRITE( ASIC, reg, val );
1.41 - WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
1.42 - reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
1.43 + case PIRQ0:
1.44 + case PIRQ1:
1.45 + case PIRQ2:
1.46 + /* Clear any interrupts */
1.47 + MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
1.48 + asic_check_cleared_events();
1.49 + break;
1.50 + case MAPLE_STATE:
1.51 + MMIO_WRITE( ASIC, reg, val );
1.52 + if( val & 1 ) {
1.53 + uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
1.54 + WARN( "Maple request initiated at %08X, halting", maple_addr );
1.55 + maple_handle_buffer( maple_addr );
1.56 + MMIO_WRITE( ASIC, reg, 0 );
1.57 + }
1.58 + break;
1.59 + case PVRDMACTL: /* Initiate PVR DMA transfer */
1.60 + if( val & 1 ) {
1.61 + uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
1.62 + uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
1.63 + char *data = alloca( count );
1.64 + uint32_t rcount = DMAC_get_buffer( 2, data, count );
1.65 + if( rcount != count )
1.66 + WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
1.67 + if( (dest_addr &0xF0000000) == 0x10000000 ) { /* TA */
1.68 + pvr2ta_write( data, rcount );
1.69 + }
1.70 + asic_event( EVENT_PVR_DMA );
1.71 + }
1.72 + break;
1.73 + default:
1.74 + MMIO_WRITE( ASIC, reg, val );
1.75 + WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
1.76 + reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
1.77 }
1.78 }
1.79
1.80 @@ -177,14 +191,16 @@
1.81 ide_write_command( (uint8_t)val );
1.82 }
1.83 break;
1.84 -
1.85 default:
1.86 + WARN( "EXTDMA write %08X <= %08X", reg, val );
1.87 +
1.88 MMIO_WRITE( EXTDMA, reg, val );
1.89 }
1.90 }
1.91
1.92 MMIO_REGION_READ_FN( EXTDMA, reg )
1.93 {
1.94 + uint32_t val;
1.95 switch( reg ) {
1.96 case IDEALTSTATUS: return idereg.status;
1.97 case IDEDATA: return ide_read_data_pio( );
1.98 @@ -198,7 +214,9 @@
1.99 ide_clear_interrupt();
1.100 return idereg.status;
1.101 default:
1.102 - return MMIO_READ( EXTDMA, reg );
1.103 + val = MMIO_READ( EXTDMA, reg );
1.104 + DEBUG( "EXTDMA read %08X => %08X", reg, val );
1.105 + return val;
1.106 }
1.107 }
1.108
.