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lxdream.org :: lxdream/src/sh4/scif.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/scif.c
changeset 428:338966c8aed0
prev54:d8b73031289c
next561:533f6b478071
author nkeynes
date Sun Oct 07 06:27:12 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix compilation warnings
file annotate diff log raw
1.1 --- a/src/sh4/scif.c Sun Jan 01 08:08:40 2006 +0000
1.2 +++ b/src/sh4/scif.c Sun Oct 07 06:27:12 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: scif.c,v 1.8 2006-01-01 08:08:40 nkeynes Exp $
1.6 + * $Id: scif.c,v 1.9 2007-10-07 06:27:12 nkeynes Exp $
1.7 * SCIF (Serial Communication Interface with FIFO) implementation - part of the
1.8 * SH4 standard on-chip peripheral set. The SCIF is hooked up to the DCs
1.9 * external serial port
1.10 @@ -130,7 +130,7 @@
1.11 #define IS_RECEIVE_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RIE)
1.12 #define IS_RECEIVE_ERROR_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & (SCSCR2_RIE|SCSCR2_REIE))
1.13 /* Receive is enabled if the RE bit is set in SCSCR2, and the ORER bit is cleared in SCLSR2 */
1.14 -#define IS_RECEIVE_ENABLED() ( (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RE) && (MMIO_READ(SCIF,SCLSR2) & SCLSR2_ORER == 0) )
1.15 +#define IS_RECEIVE_ENABLED() ( (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RE) && ((MMIO_READ(SCIF,SCLSR2) & SCLSR2_ORER) == 0) )
1.16 /* Transmit is enabled if the TE bit is set in SCSCR2 */
1.17 #define IS_TRANSMIT_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_TE)
1.18 #define IS_LOOPBACK_ENABLED() (MMIO_READ(SCIF,SCFCR2) & SCFCR2_LOOP)
1.19 @@ -393,7 +393,7 @@
1.20
1.21 if( sendq_size <= SCIF_sendq.trigger )
1.22 result |= SCFSR2_TDFE;
1.23 - else if( result & SCFSR2_TDFE == 0 && IS_TRANSMIT_IRQ_ENABLED() )
1.24 + else if( (result & SCFSR2_TDFE) == 0 && IS_TRANSMIT_IRQ_ENABLED() )
1.25 intc_clear_interrupt( INT_SCIF_TXI );
1.26
1.27 if( recvq_size >= SCIF_recvq.trigger )
1.28 @@ -481,7 +481,7 @@
1.29 serial_device->set_line_params( val );
1.30 }
1.31 tmp = MMIO_READ( SCIF, SCSMR2 );
1.32 - if( tmp & 0x03 != val & 0x03 ) {
1.33 + if( (tmp & 0x03) != (val & 0x03) ) {
1.34 /* Clock change */
1.35 SCIF_update_line_speed( );
1.36 }
1.37 @@ -502,11 +502,11 @@
1.38 */
1.39 val &= 0x00FA;
1.40 /* Clear any interrupts that just became disabled */
1.41 - if( val & SCSCR2_TIE == 0 )
1.42 + if( (val & SCSCR2_TIE) == 0 )
1.43 intc_clear_interrupt( INT_SCIF_TXI );
1.44 - if( val & SCSCR2_RIE == 0 )
1.45 + if( (val & SCSCR2_RIE) == 0 )
1.46 intc_clear_interrupt( INT_SCIF_RXI );
1.47 - if( val & (SCSCR2_RIE|SCSCR2_REIE) == 0 ) {
1.48 + if( (val & (SCSCR2_RIE|SCSCR2_REIE)) == 0 ) {
1.49 intc_clear_interrupt( INT_SCIF_ERI );
1.50 intc_clear_interrupt( INT_SCIF_BRI );
1.51 }
1.52 @@ -609,7 +609,7 @@
1.53 SCIF_recvq.head != SCIF_recvq.tail &&
1.54 SCIF_recvq_size() < SCIF_recvq.trigger ) {
1.55 uint32_t tmp = MMIO_READ( SCIF, SCFSR2 );
1.56 - if( tmp & SCFSR2_DR == 0 ) {
1.57 + if( (tmp & SCFSR2_DR) == 0 ) {
1.58 MMIO_WRITE( SCIF, SCFSR2, tmp | SCFSR2_DR );
1.59 if( IS_RECEIVE_IRQ_ENABLED() )
1.60 intc_raise_interrupt( INT_SCIF_RXI );
.