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lxdream.org :: lxdream/src/aica/armcore.h :: diff
lxdream 0.9.1
released Jun 29
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filename src/aica/armcore.h
changeset 2:42349f6ea216
next5:d85c2e81ce2d
author nkeynes
date Sat Aug 21 06:15:49 2004 +0000 (16 years ago)
permissions -rw-r--r--
last change Commit changes into cvs
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1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/aica/armcore.h Sat Aug 21 06:15:49 2004 +0000
1.3 @@ -0,0 +1,47 @@
1.4 +
1.5 +#ifndef dream_armcore_H
1.6 +#define dream_armcore_H 1
1.7 +
1.8 +#include "dream.h"
1.9 +#include <stdint.h>
1.10 +
1.11 +
1.12 +
1.13 +struct arm_registers {
1.14 + uint32_t r[16]; /* Current register bank */
1.15 +
1.16 + uint32_t cpsr;
1.17 + uint32_t spsr;
1.18 +
1.19 + /* Various banked versions of the registers. */
1.20 + uint32_t fiq_r[7]; /* FIQ bank 8..14 */
1.21 + uint32_t irq_r[2]; /* IRQ bank 13..14 */
1.22 + uint32_t und_r[2]; /* UND bank 13..14 */
1.23 + uint32_t abt_r[2]; /* ABT bank 13..14 */
1.24 + uint32_t svc_r[2]; /* SVC bank 13..14 */
1.25 + uint32_t user_r[7]; /* User/System bank 8..14 */
1.26 +
1.27 +};
1.28 +
1.29 +#define CPSR_N 0x80000000 /* Negative flag */
1.30 +#define CPSR_Z 0x40000000 /* Zero flag */
1.31 +#define CPSR_C 0x20000000 /* Carry flag */
1.32 +#define CPSR_V 0x10000000 /* Overflow flag */
1.33 +#define CPSR_I 0x00000080 /* Interrupt disable bit */
1.34 +#define CPSR_F 0x00000040 /* Fast interrupt disable bit */
1.35 +#define CPSR_T 0x00000020 /* Thumb mode */
1.36 +#define CPSR_MODE 0x0000001F /* Current execution mode */
1.37 +
1.38 +#define MODE_USER 0x00 /* User mode */
1.39 +#define MODE_FIQ 0x01 /* Fast IRQ mode */
1.40 +#define MODE_IRQ 0x02 /* IRQ mode */
1.41 +#define MODE_SV 0x03 /* Supervisor mode */
1.42 +#define MODE_ABT 0x07 /* Abort mode */
1.43 +#define MODE_UND 0x0B /* Undefined mode */
1.44 +#define MODE_SYS 0x0F /* System mode */
1.45 +
1.46 +extern struct arm_registers armr;
1.47 +
1.48 +
1.49 +
1.50 +#endif /* !dream_armcore_H */
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