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lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 2:42349f6ea216
prev1:eea311cfd33e
next15:5194dd0fdb60
author nkeynes
date Sat Aug 21 06:15:49 2004 +0000 (15 years ago)
permissions -rw-r--r--
last change Commit changes into cvs
file annotate diff log raw
1.1 --- a/src/asic.c Sat Mar 13 00:03:32 2004 +0000
1.2 +++ b/src/asic.c Sat Aug 21 06:15:49 2004 +0000
1.3 @@ -3,7 +3,9 @@
1.4 #include "mem.h"
1.5 #include "sh4/intc.h"
1.6 #include "asic.h"
1.7 +#include "dreamcast.h"
1.8 #include "maple.h"
1.9 +#include "ide.h"
1.10 #define MMIO_IMPL
1.11 #include "asic.h"
1.12 /*
1.13 @@ -39,10 +41,10 @@
1.14 MMIO_WRITE( ASIC, reg, val );
1.15 if( val & 1 ) {
1.16 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
1.17 -// maple_handle_buffer( maple_addr );
1.18 - WARN( "Maple request initiated, halting" );
1.19 + WARN( "Maple request initiated at %08X, halting", maple_addr );
1.20 + maple_handle_buffer( maple_addr );
1.21 MMIO_WRITE( ASIC, reg, 0 );
1.22 - sh4_stop();
1.23 +// dreamcast_stop();
1.24 }
1.25 break;
1.26 default:
1.27 @@ -56,6 +58,11 @@
1.28 {
1.29 int32_t val;
1.30 switch( reg ) {
1.31 + /*
1.32 + case 0x89C:
1.33 + sh4_stop();
1.34 + return 0x000000B;
1.35 + */
1.36 case PIRQ0:
1.37 case PIRQ1:
1.38 case PIRQ2:
1.39 @@ -91,13 +98,63 @@
1.40
1.41 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
1.42 {
1.43 - MMIO_WRITE( EXTDMA, reg, val );
1.44 + switch( reg ) {
1.45 + case IDEALTSTATUS: /* Device control */
1.46 + ide_write_control( val );
1.47 + break;
1.48 + case IDEDATA:
1.49 + ide_write_data_pio( val );
1.50 + break;
1.51 + case IDEFEAT:
1.52 + if( ide_can_write_regs() )
1.53 + idereg.feature = (uint8_t)val;
1.54 + break;
1.55 + case IDECOUNT:
1.56 + if( ide_can_write_regs() )
1.57 + idereg.count = (uint8_t)val;
1.58 + break;
1.59 + case IDELBA0:
1.60 + if( ide_can_write_regs() )
1.61 + idereg.lba0 = (uint8_t)val;
1.62 + break;
1.63 + case IDELBA1:
1.64 + if( ide_can_write_regs() )
1.65 + idereg.lba1 = (uint8_t)val;
1.66 + break;
1.67 + case IDELBA2:
1.68 + if( ide_can_write_regs() )
1.69 + idereg.lba2 = (uint8_t)val;
1.70 + break;
1.71 + case IDEDEV:
1.72 + if( ide_can_write_regs() )
1.73 + idereg.device = (uint8_t)val;
1.74 + break;
1.75 + case IDECMD:
1.76 + if( ide_can_write_regs() ) {
1.77 + ide_clear_interrupt();
1.78 + ide_write_command( (uint8_t)val );
1.79 + }
1.80 + break;
1.81 +
1.82 + default:
1.83 + MMIO_WRITE( EXTDMA, reg, val );
1.84 + }
1.85 }
1.86
1.87 MMIO_REGION_READ_FN( EXTDMA, reg )
1.88 {
1.89 switch( reg ) {
1.90 - case GDBUSY: return 0;
1.91 + case IDEALTSTATUS: return idereg.status;
1.92 + case IDEDATA: return ide_read_data_pio( );
1.93 + case IDEFEAT: return idereg.error;
1.94 + case IDECOUNT:return idereg.count;
1.95 + case IDELBA0: return idereg.disc;
1.96 + case IDELBA1: return idereg.lba1;
1.97 + case IDELBA2: return idereg.lba2;
1.98 + case IDEDEV: return idereg.device;
1.99 + case IDECMD:
1.100 + ide_clear_interrupt();
1.101 + return idereg.status;
1.102 default:
1.103 return MMIO_READ( EXTDMA, reg );
1.104 }
.