1.1 --- a/src/asic.c Sat Mar 13 00:03:32 2004 +0000
1.2 +++ b/src/asic.c Sat Aug 21 06:15:49 2004 +0000
1.5 #include "sh4/intc.h"
1.7 +#include "dreamcast.h"
1.14 MMIO_WRITE( ASIC, reg, val );
1.16 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
1.17 -// maple_handle_buffer( maple_addr );
1.18 - WARN( "Maple request initiated, halting" );
1.19 + WARN( "Maple request initiated at %08X, halting", maple_addr );
1.20 + maple_handle_buffer( maple_addr );
1.21 MMIO_WRITE( ASIC, reg, 0 );
1.23 +// dreamcast_stop();
1.41 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
1.43 - MMIO_WRITE( EXTDMA, reg, val );
1.45 + case IDEALTSTATUS: /* Device control */
1.46 + ide_write_control( val );
1.49 + ide_write_data_pio( val );
1.52 + if( ide_can_write_regs() )
1.53 + idereg.feature = (uint8_t)val;
1.56 + if( ide_can_write_regs() )
1.57 + idereg.count = (uint8_t)val;
1.60 + if( ide_can_write_regs() )
1.61 + idereg.lba0 = (uint8_t)val;
1.64 + if( ide_can_write_regs() )
1.65 + idereg.lba1 = (uint8_t)val;
1.68 + if( ide_can_write_regs() )
1.69 + idereg.lba2 = (uint8_t)val;
1.72 + if( ide_can_write_regs() )
1.73 + idereg.device = (uint8_t)val;
1.76 + if( ide_can_write_regs() ) {
1.77 + ide_clear_interrupt();
1.78 + ide_write_command( (uint8_t)val );
1.83 + MMIO_WRITE( EXTDMA, reg, val );
1.87 MMIO_REGION_READ_FN( EXTDMA, reg )
1.90 - case GDBUSY: return 0;
1.91 + case IDEALTSTATUS: return idereg.status;
1.92 + case IDEDATA: return ide_read_data_pio( );
1.93 + case IDEFEAT: return idereg.error;
1.94 + case IDECOUNT:return idereg.count;
1.95 + case IDELBA0: return idereg.disc;
1.96 + case IDELBA1: return idereg.lba1;
1.97 + case IDELBA2: return idereg.lba2;
1.98 + case IDEDEV: return idereg.device;
1.100 + ide_clear_interrupt();
1.101 + return idereg.status;
1.103 return MMIO_READ( EXTDMA, reg );