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lxdream 0.9.1
released Jun 29
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filename src/gdrom/ide.h
changeset 2:42349f6ea216
next31:495e480360d7
author nkeynes
date Sat Aug 21 06:15:49 2004 +0000 (16 years ago)
permissions -rw-r--r--
last change Commit changes into cvs
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1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/gdrom/ide.h Sat Aug 21 06:15:49 2004 +0000
1.3 @@ -0,0 +1,91 @@
1.4 +/*
1.5 + * ide.h 31 Mar 2004 - IDE Interface definitions
1.6 + *
1.7 + * Copyright (c) 2004 Nathan Keynes. Distribution and modification permitted
1.8 + * under the terms of the GNU General Public License version 2 or later.
1.9 + *
1.10 + * This file defines the interface and structures of the dreamcast's IDE port.
1.11 + * Note that the register definitions are in asic.h, as the registers fall into
1.12 + * the general ASIC ranges (and I don't want to use smaller pages at this
1.13 + * stage). The registers here are exactly as per the ATA specifications, which
1.14 + * makes things a little easier.
1.15 + */
1.16 +#ifndef dream_ide_H
1.17 +#define dream_ide_H 1
1.18 +
1.19 +#include "dream.h"
1.20 +
1.21 +struct ide_registers {
1.22 + uint8_t status; /* A05F709C + A05F7018 Read-only */
1.23 + uint8_t control; /* A05F7018 Write-only 01110 */
1.24 + uint8_t error; /* A05F7084 Read-only 10001 */
1.25 + uint8_t feature; /* A05F7084 Write-only 10001 */
1.26 + uint8_t count; /* A05F7088 Read/Write 10010 */
1.27 + uint8_t disc; /* A05F708C Read-only 10011 */
1.28 + uint8_t lba0; /* A05F708C Write-only 10011 (NB: Presumed, TBV */
1.29 + uint8_t lba1; /* A05F7090 Read/Write 10100 */
1.30 + uint8_t lba2; /* A05F7094 Read/Write 10101 */
1.31 + uint8_t device; /* A05F7098 Read/Write 10110 */
1.32 + uint8_t command; /* A05F709C Write-only 10111 */
1.33 +
1.34 + /* We don't keep the data register per se, rather the currently pending
1.35 + * data is kept here and read out a byte at a time (in PIO mode) or all at
1.36 + * once (in DMA mode). The IDE routines are responsible for managing this
1.37 + * memory. If dataptr == NULL, there is no data available.
1.38 + */
1.39 + char *data;
1.40 + uint16_t *readptr, *writeptr;
1.41 + int datalen;
1.42 +};
1.43 +
1.44 +#define IDE_ST_BUSY 0x80
1.45 +#define IDE_ST_READY 0x40
1.46 +#define IDE_ST_SERV 0x10
1.47 +#define IDE_ST_DATA 0x08
1.48 +#define IDE_ST_ERROR 0x01
1.49 +
1.50 +#define IDE_CTL_RESET 0x04
1.51 +#define IDE_CTL_IRQEN 0x02 /* IRQ enabled when == 0 */
1.52 +
1.53 +#define IDE_CMD_RESET_DEVICE 0x08
1.54 +#define IDE_CMD_PACKET 0xA0
1.55 +#define IDE_CMD_IDENTIFY_PACKET_DEVICE 0xA1
1.56 +#define IDE_CMD_SERVICE 0xA2
1.57 +#define IDE_CMD_SET_FEATURE 0xEF
1.58 +
1.59 +/* The disc register indicates the current contents of the drive. When open
1.60 + * contains 0x06.
1.61 + */
1.62 +#define IDE_DISC_AUDIO 0x00
1.63 +#define IDE_DISC_NONE 0x06
1.64 +#define IDE_DISC_CDROM 0x20
1.65 +#define IDE_DISC_GDROM 0x80
1.66 +#define IDE_DISC_READY 0x01 /* ored with above */
1.67 +#define IDE_DISC_IDLE 0x02 /* ie spun-down */
1.68 +
1.69 +#define PKT_CMD_RESET 0x00 /* Wild-ass guess */
1.70 +#define PKT_CMD_IDENTIFY 0x11
1.71 +
1.72 +extern struct ide_registers idereg;
1.73 +
1.74 +/* Note: control can be written at any time - all other registers are writable
1.75 + * only when ide_can_write_regs() is true
1.76 + */
1.77 +#define ide_can_write_regs() ((idereg.status&0x88)==0)
1.78 +
1.79 +/* Called upon:
1.80 + * a) Writing the command register
1.81 + * b) Reading the status (but not altstatus) register
1.82 + * (whether this actually has any effect an the ASIC event is TBD)
1.83 + */
1.84 +void ide_clear_interrupt(void);
1.85 +
1.86 +void ide_reset(void);
1.87 +
1.88 +uint16_t ide_read_data_pio(void);
1.89 +void ide_write_data_pio( uint16_t value );
1.90 +void ide_write_buffer( char * );
1.91 +
1.92 +void ide_write_command( uint8_t command );
1.93 +void ide_write_control( uint8_t value );
1.94 +#endif
.