1.1 --- a/src/sh4/sh4core.h	Sat Mar 13 00:03:32 2004 +0000
     1.2 +++ b/src/sh4/sh4core.h	Sat Aug 21 06:15:49 2004 +0000
     1.3 @@ -22,9 +22,13 @@
     1.4      uint32_t m, q, s, t; /* really boolean - 0 or 1 */
     1.5      float fr[2][16];
     1.6  
     1.7 +    int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
     1.8 +    
     1.9      uint32_t new_pc; /* Not a real register, but used to handle delay slots */
    1.10      uint32_t icount; /* Also not a real register, instruction counter */
    1.11      uint32_t int_pending; /* flag set by the INTC = pending priority level */
    1.12 +    int in_delay_slot; /* flag to indicate the current instruction is in
    1.13 +                             * a delay slot (certain rules apply) */
    1.14  };
    1.15  
    1.16  extern struct sh4_registers sh4r;
    1.17 @@ -66,7 +70,7 @@
    1.18  
    1.19  #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
    1.20  #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
    1.21 -#define SH4_INT_PENDING() (sh4r.int_pending)
    1.22 +#define SH4_INT_PENDING() (sh4r.int_pending && !sh4r.in_delay_slot)
    1.23  
    1.24  #define FPSCR_FR     0x00200000 /* FPU register bank */
    1.25  #define FPSCR_SZ     0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
    1.26 @@ -82,6 +86,7 @@
    1.27  #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
    1.28  
    1.29  #define FR sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]
    1.30 +#define XF sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]
    1.31  
    1.32  /* Exceptions (for use with sh4_raise_exception) */
    1.33  
    1.34 @@ -100,7 +105,7 @@
    1.35  #define EX_FPU_DISABLED        0x800, 0x100
    1.36  #define EX_SLOT_FPU_DISABLED   0x820, 0x100
    1.37  
    1.38 -
    1.39 +#define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
    1.40  
    1.41  #ifdef __cplusplus
    1.42  }