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lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 931:430048ea8b71
prev929:fd8cb0c82f5f
next933:880c37bb1909
author nkeynes
date Tue Dec 23 05:48:05 2008 +0000 (13 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change More refactoring and general cleanup. Most things should be working again now.
Split off cache and start real implementation, breaking save states in the process
file annotate diff log raw
1.1 --- a/src/sh4/mmu.c Sat Dec 20 03:01:40 2008 +0000
1.2 +++ b/src/sh4/mmu.c Tue Dec 23 05:48:05 2008 +0000
1.3 @@ -23,6 +23,7 @@
1.4 #include "sh4/sh4core.h"
1.5 #include "sh4/sh4trans.h"
1.6 #include "mem.h"
1.7 +#include "mmu.h"
1.8
1.9 #ifdef HAVE_FRAME_ADDRESS
1.10 #define RETURN_VIA(exc) do{ *(((void **)__builtin_frame_address(0))+1) = exc; return; } while(0)
1.11 @@ -30,8 +31,6 @@
1.12 #define RETURN_VIA(exc) return MMU_VMA_ERROR
1.13 #endif
1.14
1.15 -#define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
1.16 -
1.17 /* The MMU (practically unique in the system) is allowed to raise exceptions
1.18 * directly, with a return code indicating that one was raised and the caller
1.19 * had better behave appropriately.
1.20 @@ -68,52 +67,6 @@
1.21 #define OCRAM_START (0x1C000000>>LXDREAM_PAGE_BITS)
1.22 #define OCRAM_END (0x20000000>>LXDREAM_PAGE_BITS)
1.23
1.24 -#define ITLB_ENTRY_COUNT 4
1.25 -#define UTLB_ENTRY_COUNT 64
1.26 -
1.27 -/* Entry address */
1.28 -#define TLB_VALID 0x00000100
1.29 -#define TLB_USERMODE 0x00000040
1.30 -#define TLB_WRITABLE 0x00000020
1.31 -#define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
1.32 -#define TLB_SIZE_MASK 0x00000090
1.33 -#define TLB_SIZE_1K 0x00000000
1.34 -#define TLB_SIZE_4K 0x00000010
1.35 -#define TLB_SIZE_64K 0x00000080
1.36 -#define TLB_SIZE_1M 0x00000090
1.37 -#define TLB_CACHEABLE 0x00000008
1.38 -#define TLB_DIRTY 0x00000004
1.39 -#define TLB_SHARE 0x00000002
1.40 -#define TLB_WRITETHRU 0x00000001
1.41 -
1.42 -#define MASK_1K 0xFFFFFC00
1.43 -#define MASK_4K 0xFFFFF000
1.44 -#define MASK_64K 0xFFFF0000
1.45 -#define MASK_1M 0xFFF00000
1.46 -
1.47 -struct itlb_entry {
1.48 - sh4addr_t vpn; // Virtual Page Number
1.49 - uint32_t asid; // Process ID
1.50 - uint32_t mask;
1.51 - sh4addr_t ppn; // Physical Page Number
1.52 - uint32_t flags;
1.53 -};
1.54 -
1.55 -struct utlb_entry {
1.56 - sh4addr_t vpn; // Virtual Page Number
1.57 - uint32_t mask; // Page size mask
1.58 - uint32_t asid; // Process ID
1.59 - sh4addr_t ppn; // Physical Page Number
1.60 - uint32_t flags;
1.61 - uint32_t pcmcia; // extra pcmcia data - not used
1.62 -};
1.63 -
1.64 -struct utlb_sort_entry {
1.65 - sh4addr_t key; // Masked VPN + ASID
1.66 - uint32_t mask; // Mask + 0x00FF
1.67 - int entryNo;
1.68 -};
1.69 -
1.70
1.71 static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
1.72 static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
1.73 @@ -129,8 +82,7 @@
1.74
1.75 static void mmu_invalidate_tlb();
1.76 static void mmu_utlb_sorted_reset();
1.77 -static void mmu_utlb_sorted_reload();
1.78 -
1.79 +static void mmu_utlb_sorted_reload();
1.80
1.81 static uint32_t get_mask_for_flags( uint32_t flags )
1.82 {
1.83 @@ -199,7 +151,7 @@
1.84 }
1.85 break;
1.86 case CCR:
1.87 - mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA|CCR_OCE) );
1.88 + CCN_set_cache_control( val );
1.89 val &= 0x81A7;
1.90 break;
1.91 case MMUUNK1:
1.92 @@ -229,7 +181,6 @@
1.93
1.94 void MMU_init()
1.95 {
1.96 - cache = mem_alloc_pages(2);
1.97 }
1.98
1.99 void MMU_reset()
1.100 @@ -241,7 +192,6 @@
1.101
1.102 void MMU_save_state( FILE *f )
1.103 {
1.104 - fwrite( cache, 4096, 2, f );
1.105 fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
1.106 fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
1.107 fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
1.108 @@ -252,13 +202,6 @@
1.109
1.110 int MMU_load_state( FILE *f )
1.111 {
1.112 - /* Setup the cache mode according to the saved register value
1.113 - * (mem_load runs before this point to load all MMIO data)
1.114 - */
1.115 - mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
1.116 - if( fread( cache, 4096, 2, f ) != 2 ) {
1.117 - return 1;
1.118 - }
1.119 if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
1.120 return 1;
1.121 }
1.122 @@ -281,24 +224,6 @@
1.123 return 0;
1.124 }
1.125
1.126 -void mmu_set_cache_mode( int mode )
1.127 -{
1.128 - uint32_t i;
1.129 - switch( mode ) {
1.130 - case MEM_OC_INDEX0: /* OIX=0 */
1.131 - for( i=OCRAM_START; i<OCRAM_END; i++ )
1.132 - page_map[i] = cache + ((i&0x02)<<(LXDREAM_PAGE_BITS-1));
1.133 - break;
1.134 - case MEM_OC_INDEX1: /* OIX=1 */
1.135 - for( i=OCRAM_START; i<OCRAM_END; i++ )
1.136 - page_map[i] = cache + ((i&0x02000000)>>(25-LXDREAM_PAGE_BITS));
1.137 - break;
1.138 - default: /* disabled */
1.139 - for( i=OCRAM_START; i<OCRAM_END; i++ )
1.140 - page_map[i] = NULL;
1.141 - break;
1.142 - }
1.143 -}
1.144
1.145 /******************* Sorted TLB data structure ****************/
1.146 /*
1.147 @@ -1091,7 +1016,8 @@
1.148 uint32_t hi = MMIO_READ( MMU, QACR0 + (queue>>1)) << 24;
1.149 sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
1.150 sh4addr_t target = (addr&0x03FFFFE0) | hi;
1.151 - mem_copy_to_sh4( target, src, 32 );
1.152 + ext_address_space[target>>12]->write_burst( target, src );
1.153 +// mem_copy_to_sh4( target, src, 32 );
1.154 }
1.155
1.156 gboolean FASTCALL sh4_flush_store_queue_mmu( sh4addr_t addr )
1.157 @@ -1133,7 +1059,8 @@
1.158 (addr & (~mmu_utlb[entryNo].mask))) & 0xFFFFFFE0;
1.159 }
1.160
1.161 - mem_copy_to_sh4( target, src, 32 );
1.162 + ext_address_space[target>>12]->write_burst( target, src );
1.163 + // mem_copy_to_sh4( target, src, 32 );
1.164 return TRUE;
1.165 }
1.166
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