1.1 --- a/src/sh4/sh4x86.c	Thu May 15 10:22:39 2008 +0000
     1.2 +++ b/src/sh4/sh4x86.c	Sun May 25 21:01:55 2008 +0000
     1.3 @@ -750,7 +750,7 @@
     1.4                              case 0x6:
     1.5                                  { /* STS FPSCR, Rn */
     1.6                                  uint32_t Rn = ((ir>>8)&0xF); 
     1.7 -                                COUNT_INST(I_STS);
     1.8 +                                COUNT_INST(I_STSFPSCR);
     1.9                                  check_fpuen();
    1.10                                  load_spreg( R_EAX, R_FPSCR );
    1.11                                  store_reg( R_EAX, Rn );
    1.12 @@ -1488,7 +1488,7 @@
    1.13                              case 0x6:
    1.14                                  { /* STS.L FPSCR, @-Rn */
    1.15                                  uint32_t Rn = ((ir>>8)&0xF); 
    1.16 -                                COUNT_INST(I_STSM);
    1.17 +                                COUNT_INST(I_STSFPSCRM);
    1.18                                  check_fpuen();
    1.19                                  load_reg( R_EAX, Rn );
    1.20                                  check_walign32( R_EAX );
    1.21 @@ -1768,7 +1768,7 @@
    1.22                              case 0x6:
    1.23                                  { /* LDS.L @Rm+, FPSCR */
    1.24                                  uint32_t Rm = ((ir>>8)&0xF); 
    1.25 -                                COUNT_INST(I_LDS);
    1.26 +                                COUNT_INST(I_LDSFPSCRM);
    1.27                                  check_fpuen();
    1.28                                  load_reg( R_EAX, Rm );
    1.29                                  check_ralign32( R_EAX );
    1.30 @@ -2020,7 +2020,7 @@
    1.31                              case 0x6:
    1.32                                  { /* LDS Rm, FPSCR */
    1.33                                  uint32_t Rm = ((ir>>8)&0xF); 
    1.34 -                                COUNT_INST(I_LDS);
    1.35 +                                COUNT_INST(I_LDSFPSCR);
    1.36                                  check_fpuen();
    1.37                                  load_reg( R_EAX, Rm );
    1.38                                  call_func1( sh4_write_fpscr, R_EAX );
    1.39 @@ -3296,18 +3296,11 @@
    1.40                          { /* FMOV FRm, FRn */
    1.41                          uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
    1.42                          COUNT_INST(I_FMOV1);
    1.43 -                        /* As horrible as this looks, it's actually covering 5 separate cases:
    1.44 -                         * 1. 32-bit fr-to-fr (PR=0)
    1.45 -                         * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
    1.46 -                         * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
    1.47 -                         * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
    1.48 -                         * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
    1.49 -                         */
    1.50                          check_fpuen();
    1.51                          load_spreg( R_ECX, R_FPSCR );
    1.52                          TEST_imm32_r32( FPSCR_SZ, R_ECX );
    1.53                          JNE_rel8(doublesize);
    1.54 -                        load_fr( R_EAX, FRm ); // PR=0 branch
    1.55 +                        load_fr( R_EAX, FRm ); // SZ=0 branch
    1.56                          store_fr( R_EAX, FRn );
    1.57                          JMP_rel8(end);
    1.58                          JMP_TARGET(doublesize);