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lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 244:4c2b7291d3b0
prev240:9ae4bd697292
next255:ade289880b8d
author nkeynes
date Tue Dec 19 09:51:35 2006 +0000 (13 years ago)
permissions -rw-r--r--
last change First cut of port 576890 (sysreset) and ide enable/disable
file annotate diff log raw
1.1 --- a/src/asic.c Fri Dec 15 10:18:39 2006 +0000
1.2 +++ b/src/asic.c Tue Dec 19 09:51:35 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: asic.c,v 1.20 2006-12-15 10:18:39 nkeynes Exp $
1.6 + * $Id: asic.c,v 1.21 2006-12-19 09:51:35 nkeynes Exp $
1.7 *
1.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
1.9 * and DMA).
1.10 @@ -213,6 +213,13 @@
1.11 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
1.12 asic_check_cleared_events();
1.13 break;
1.14 + case SYSRESET:
1.15 + if( val == 0x7611 ) {
1.16 + dreamcast_reset();
1.17 + } else {
1.18 + WARN( "Unknown value %08X written to SYSRESET port", val );
1.19 + }
1.20 + break;
1.21 case MAPLE_STATE:
1.22 MMIO_WRITE( ASIC, reg, val );
1.23 if( val & 1 ) {
1.24 @@ -279,6 +286,10 @@
1.25
1.26 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
1.27 {
1.28 + if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
1.29 + return; /* disabled */
1.30 + }
1.31 +
1.32 switch( reg ) {
1.33 case IDEALTSTATUS: /* Device control */
1.34 ide_write_control( val );
1.35 @@ -321,6 +332,15 @@
1.36 MMIO_WRITE( EXTDMA, reg, val );
1.37 asic_ide_dma_transfer( );
1.38 break;
1.39 + case IDEACTIVATE:
1.40 + if( val == 0x001FFFFF ) {
1.41 + idereg.interface_enabled = TRUE;
1.42 + /* Conventional wisdom says that this is necessary but not
1.43 + * sufficient to enable the IDE interface.
1.44 + */
1.45 + } else if( val == 0x000042FE ) {
1.46 + idereg.interface_enabled = FALSE;
1.47 + }
1.48 default:
1.49 MMIO_WRITE( EXTDMA, reg, val );
1.50 }
1.51 @@ -329,6 +349,10 @@
1.52 MMIO_REGION_READ_FN( EXTDMA, reg )
1.53 {
1.54 uint32_t val;
1.55 + if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
1.56 + return 0xFFFFFFFF; /* disabled */
1.57 + }
1.58 +
1.59 switch( reg ) {
1.60 case IDEALTSTATUS:
1.61 val = idereg.status;
.