filename | src/xlat/x86/x86op.h |
changeset | 1112:4cac5e474d4c |
prev | 1071:182cfe43c09e |
next | 1147:e04e4af64626 |
author | nkeynes |
date | Tue Jul 13 18:23:16 2010 +1000 (13 years ago) |
permissions | -rw-r--r-- |
last change | Rearrange the main translation loop to allow translated blocks to jump directly to their successors without needing to return to the main loop in between. Shaves about 6% off the core runtime. |
file | annotate | diff | log | raw |
1.1 --- a/src/xlat/x86/x86op.h Tue Jul 21 20:21:52 2009 +10001.2 +++ b/src/xlat/x86/x86op.h Tue Jul 13 18:23:16 2010 +10001.3 @@ -314,6 +314,7 @@1.4 #define x86_encode_opcode32(opcode,reg) x86_encode_opcodereg(0,opcode,reg)1.5 #define x86_encode_r32_rm32(opcode,rr,rb) x86_encode_reg_rm(0,opcode,rr,rb)1.6 #define x86_encode_r64_rm64(opcode,rr,rb) x86_encode_reg_rm(PREF_REXW,opcode,rr,rb)1.7 +#define x86_encode_rptr_rmptr(opcode,rr,rb) x86_encode_reg_rm(PREF_PTR,opcode,rr,rb)1.8 #define x86_encode_r32_mem32(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(0,opcode,rr,rb,rx,ss,disp32)1.9 #define x86_encode_r64_mem64(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,rb,rx,ss,disp32)1.10 #define x86_encode_rptr_memptr(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(PREF_PTR,opcode,rr,rb,rx,ss,disp32)1.11 @@ -397,8 +398,10 @@1.12 #define CMPB_imms_rbpdisp(imm,disp) x86_encode_r32_rbpdisp32(0x80, 7, disp); OP(imm)1.13 #define CMPB_r8_r8(r1,r2) x86_encode_r32_rm32(0x38, r1, r2)1.14 #define CMPL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 7, imm, r1)1.15 +#define CMPL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83, 0x81, 7, imm, rb, d)1.16 #define CMPL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 7, imm, disp)1.17 #define CMPL_r32_r32(r1,r2) x86_encode_r32_rm32(0x39, r1, r2)1.18 +#define CMPL_r32_r32disp(r1,r2,dsp) x86_encode_r32_mem32disp32(0x39, r1, r2, dsp)1.19 #define CMPL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x39, r1, disp)1.20 #define CMPL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x3B, r1, disp)1.21 #define CMPQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 7, imm, r1)1.22 @@ -423,7 +426,7 @@1.23 #define LEAL_sib_r32(ss,ii,bb,d,r1) x86_encode_r32_mem32(0x8D, r1, bb, ii, ss, d)1.24 #define LEAQ_r64disp_r64(r1,disp,r2) x86_encode_r64_mem64(0x8D, r2, r1, -1, 0, disp)1.25 #define LEAQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp64(0x8D, r1, disp)1.26 -#define LEAP_rptrdisp_rptr(r1,d,r2) x86_encode_rptr_memptr(0x8D, r2, r1, -1, 0, disp)1.27 +#define LEAP_rptrdisp_rptr(r1,d,r2) x86_encode_rptr_memptr(0x8D, r2, r1, -1, 0, d)1.28 #define LEAP_rbpdisp_rptr(disp,r1) x86_encode_rptr_memptr(0x8D, r1, REG_RBP, -1, 0, disp)1.29 #define LEAP_sib_rptr(ss,ii,bb,d,r1) x86_encode_rptr_memptr(0x8D, r1, bb, ii, ss, d)1.31 @@ -562,6 +565,7 @@1.32 #define TESTL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x85, r1, disp) /* Same OP */1.33 #define TESTQ_imms_r64(imm,r1) x86_encode_r64_rm64(0xF7, 0, r1); OP32(imm)1.34 #define TESTQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x85, r1, r2)1.35 +#define TESTP_rptr_rptr(r1,r2) x86_encode_rptr_rmptr(0x85, r1, r2)1.37 #define XCHGB_r8_r8(r1,r2) x86_encode_r32_rm32(0x86, r1, r2)1.38 #define XCHGL_r32_r32(r1,r2) x86_encode_r32_rm32(0x87, r1, r2)1.39 @@ -586,12 +590,13 @@1.40 #define JCC_cc_rel8(cc,rel) OP(0x70+(cc)); OP(rel)1.41 #define JCC_cc_rel32(cc,rel) OP(0x0F); OP(0x80+(cc)); OP32(rel)1.42 #define JCC_cc_rel(cc,rel) if( IS_INT8(rel) ) { JCC_cc_rel8(cc,(int8_t)rel); } else { JCC_cc_rel32(cc,rel); }1.43 +#define JCC_cc_prerel(cc,rel) if( IS_INT8(rel) ) { JCC_cc_rel8(cc,(int8_t)((rel)-2)); } else { JCC_cc_rel32(cc,((rel)-6)); }1.45 #define JMP_rel8(rel) OP(0xEB); OP(rel)1.46 #define JMP_rel32(rel) OP(0xE9); OP32(rel)1.47 #define JMP_rel(rel) if( IS_INT8(rel) ) { JMP_rel8((int8_t)rel); } else { JMP_rel32(rel); }1.48 #define JMP_prerel(rel) if( IS_INT8(((int32_t)rel)-2) ) { JMP_rel8(((int8_t)rel)-2); } else { JMP_rel32(((int32_t)rel)-5); }1.49 -#define JMP_r32(r1,disp) x86_encode_r32_rm32(0xFF, 4, r1)1.50 +#define JMP_rptr(r1) x86_encode_r32_rm32(0xFF, 4, r1)1.51 #define JMP_r32disp(r1,disp) x86_encode_r32_mem32disp32(0xFF, 4, r1, disp)1.52 #define RET() OP(0xC3)1.53 #define RET_imm(imm) OP(0xC2); OP16(imm)
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