filename | src/asic.c |
changeset | 736:a02d1475ccfd |
prev | 728:4dfc293b9d96 |
next | 753:1fe39c3a9bbc |
author | nkeynes |
date | Sat Jul 19 00:56:54 2008 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Add uninstall hook for pixmaps Fix distcheck in the test dir Add missing joy_linux.h to dist |
file | annotate | diff | log | raw |
1.1 --- a/src/asic.c Sun Jul 06 05:30:32 2008 +00001.2 +++ b/src/asic.c Sat Jul 19 00:56:54 2008 +00001.3 @@ -52,7 +52,7 @@1.4 static uint32_t g2_update_fifo_status( uint32_t slice_cycle );1.6 struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,1.7 - NULL, asic_save_state, asic_load_state };1.8 + NULL, asic_save_state, asic_load_state };1.10 #define G2_BIT5_TICKS 601.11 #define G2_BIT4_TICKS 1601.12 @@ -73,33 +73,33 @@1.13 {1.14 g2_update_fifo_status(nanosecs);1.15 if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {1.16 - g2_state.bit5_off_timer = -1;1.17 + g2_state.bit5_off_timer = -1;1.18 } else {1.19 - g2_state.bit5_off_timer -= nanosecs;1.20 + g2_state.bit5_off_timer -= nanosecs;1.21 }1.23 if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {1.24 - g2_state.bit4_off_timer = -1;1.25 + g2_state.bit4_off_timer = -1;1.26 } else {1.27 - g2_state.bit4_off_timer -= nanosecs;1.28 + g2_state.bit4_off_timer -= nanosecs;1.29 }1.30 if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {1.31 - g2_state.bit4_on_timer = -1;1.32 + g2_state.bit4_on_timer = -1;1.33 } else {1.34 - g2_state.bit4_on_timer -= nanosecs;1.35 + g2_state.bit4_on_timer -= nanosecs;1.36 }1.37 -1.38 +1.39 if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {1.40 - g2_state.bit0_off_timer = -1;1.41 + g2_state.bit0_off_timer = -1;1.42 } else {1.43 - g2_state.bit0_off_timer -= nanosecs;1.44 + g2_state.bit0_off_timer -= nanosecs;1.45 }1.46 if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {1.47 - g2_state.bit0_on_timer = -1;1.48 + g2_state.bit0_on_timer = -1;1.49 } else {1.50 - g2_state.bit0_on_timer -= nanosecs;1.51 + g2_state.bit0_on_timer -= nanosecs;1.52 }1.53 -1.54 +1.55 return nanosecs;1.56 }1.58 @@ -123,9 +123,9 @@1.59 static int asic_load_state( FILE *f )1.60 {1.61 if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )1.62 - return 1;1.63 + return 1;1.64 else1.65 - return 0;1.66 + return 0;1.67 }1.70 @@ -146,29 +146,29 @@1.71 void asic_g2_write_word()1.72 {1.73 if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {1.74 - g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;1.75 + g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;1.76 } else {1.77 - g2_state.bit5_off_timer += G2_BIT5_TICKS;1.78 + g2_state.bit5_off_timer += G2_BIT5_TICKS;1.79 }1.81 if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {1.82 - g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;1.83 + g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;1.84 }1.86 if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {1.87 - g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;1.88 + g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;1.89 } else {1.90 - g2_state.bit4_off_timer += G2_BIT4_TICKS;1.91 + g2_state.bit4_off_timer += G2_BIT4_TICKS;1.92 }1.94 if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {1.95 - g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;1.96 + g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;1.97 }1.99 if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {1.100 - g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;1.101 + g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;1.102 } else {1.103 - g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;1.104 + g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;1.105 }1.107 MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );1.108 @@ -178,25 +178,25 @@1.109 {1.110 uint32_t val = MMIO_READ( ASIC, G2STATUS );1.111 if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {1.112 - val = val & (~0x20);1.113 - g2_state.bit5_off_timer = -1;1.114 + val = val & (~0x20);1.115 + g2_state.bit5_off_timer = -1;1.116 }1.117 if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {1.118 - val = val | 0x10;1.119 - g2_state.bit4_on_timer = -1;1.120 + val = val | 0x10;1.121 + g2_state.bit4_on_timer = -1;1.122 }1.123 if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {1.124 - val = val & (~0x10);1.125 - g2_state.bit4_off_timer = -1;1.126 + val = val & (~0x10);1.127 + g2_state.bit4_off_timer = -1;1.128 }1.130 if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {1.131 - val = val | 0x01;1.132 - g2_state.bit0_on_timer = -1;1.133 + val = val | 0x01;1.134 + g2_state.bit0_on_timer = -1;1.135 }1.136 if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {1.137 - val = val & (~0x01);1.138 - g2_state.bit0_off_timer = -1;1.139 + val = val & (~0x01);1.140 + g2_state.bit0_off_timer = -1;1.141 }1.143 MMIO_WRITE( ASIC, G2STATUS, val );1.144 @@ -221,9 +221,9 @@1.145 intc_raise_interrupt( INT_IRQ9 );1.147 if( event >= 64 ) { /* Third word */1.148 - asic_event( EVENT_CASCADE2 );1.149 + asic_event( EVENT_CASCADE2 );1.150 } else if( event >= 32 ) { /* Second word */1.151 - asic_event( EVENT_CASCADE1 );1.152 + asic_event( EVENT_CASCADE1 );1.153 }1.154 }1.156 @@ -232,14 +232,14 @@1.157 uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));1.158 MMIO_WRITE( ASIC, PIRQ0 + offset, result );1.159 if( result == 0 ) {1.160 - /* clear cascades if necessary */1.161 - if( event >= 64 ) {1.162 - MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );1.163 - } else if( event >= 32 ) {1.164 - MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );1.165 - }1.166 + /* clear cascades if necessary */1.167 + if( event >= 64 ) {1.168 + MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );1.169 + } else if( event >= 32 ) {1.170 + MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );1.171 + }1.172 }1.173 -1.174 +1.175 asic_check_cleared_events();1.176 }1.178 @@ -248,17 +248,17 @@1.179 int i, setA = 0, setB = 0, setC = 0;1.180 uint32_t bits;1.181 for( i=0; i<12; i+=4 ) {1.182 - bits = MMIO_READ( ASIC, PIRQ0 + i );1.183 - setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));1.184 - setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));1.185 - setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));1.186 + bits = MMIO_READ( ASIC, PIRQ0 + i );1.187 + setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));1.188 + setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));1.189 + setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));1.190 }1.191 if( setA == 0 )1.192 - intc_clear_interrupt( INT_IRQ13 );1.193 + intc_clear_interrupt( INT_IRQ13 );1.194 if( setB == 0 )1.195 - intc_clear_interrupt( INT_IRQ11 );1.196 + intc_clear_interrupt( INT_IRQ11 );1.197 if( setC == 0 )1.198 - intc_clear_interrupt( INT_IRQ9 );1.199 + intc_clear_interrupt( INT_IRQ9 );1.200 }1.202 void asic_event_mask_changed( )1.203 @@ -266,23 +266,23 @@1.204 int i, setA = 0, setB = 0, setC = 0;1.205 uint32_t bits;1.206 for( i=0; i<12; i+=4 ) {1.207 - bits = MMIO_READ( ASIC, PIRQ0 + i );1.208 - setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));1.209 - setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));1.210 - setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));1.211 + bits = MMIO_READ( ASIC, PIRQ0 + i );1.212 + setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));1.213 + setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));1.214 + setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));1.215 }1.216 if( setA == 0 )1.217 - intc_clear_interrupt( INT_IRQ13 );1.218 + intc_clear_interrupt( INT_IRQ13 );1.219 else1.220 - intc_raise_interrupt( INT_IRQ13 );1.221 + intc_raise_interrupt( INT_IRQ13 );1.222 if( setB == 0 )1.223 - intc_clear_interrupt( INT_IRQ11 );1.224 + intc_clear_interrupt( INT_IRQ11 );1.225 else1.226 - intc_raise_interrupt( INT_IRQ11 );1.227 + intc_raise_interrupt( INT_IRQ11 );1.228 if( setC == 0 )1.229 - intc_clear_interrupt( INT_IRQ9 );1.230 + intc_clear_interrupt( INT_IRQ9 );1.231 else1.232 - intc_raise_interrupt( INT_IRQ9 );1.233 + intc_raise_interrupt( INT_IRQ9 );1.234 }1.236 void g2_dma_transfer( int channel )1.237 @@ -290,44 +290,44 @@1.238 uint32_t offset = channel << 5;1.240 if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {1.241 - if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {1.242 - uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );1.243 - uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );1.244 - uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;1.245 - uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );1.246 - // uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );1.247 - unsigned char buf[length];1.248 - if( dir == 0 ) { /* SH4 to device */1.249 - mem_copy_from_sh4( buf, sh4addr, length );1.250 - mem_copy_to_sh4( extaddr, buf, length );1.251 - } else { /* Device to SH4 */1.252 - mem_copy_from_sh4( buf, extaddr, length );1.253 - mem_copy_to_sh4( sh4addr, buf, length );1.254 - }1.255 - MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );1.256 - asic_event( EVENT_G2_DMA0 + channel );1.257 - } else {1.258 - MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );1.259 - }1.260 + if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {1.261 + uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );1.262 + uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );1.263 + uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;1.264 + uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );1.265 + // uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );1.266 + unsigned char buf[length];1.267 + if( dir == 0 ) { /* SH4 to device */1.268 + mem_copy_from_sh4( buf, sh4addr, length );1.269 + mem_copy_to_sh4( extaddr, buf, length );1.270 + } else { /* Device to SH4 */1.271 + mem_copy_from_sh4( buf, extaddr, length );1.272 + mem_copy_to_sh4( sh4addr, buf, length );1.273 + }1.274 + MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );1.275 + asic_event( EVENT_G2_DMA0 + channel );1.276 + } else {1.277 + MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );1.278 + }1.279 }1.280 }1.282 void asic_ide_dma_transfer( )1.283 {1.284 if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {1.285 - if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {1.286 - MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );1.287 -1.288 - uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );1.289 - uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );1.290 - // int dir = MMIO_READ( EXTDMA, IDEDMADIR );1.291 -1.292 - uint32_t xfer = ide_read_data_dma( addr, length );1.293 - MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );1.294 - MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );1.295 - } else { /* 0 */1.296 - MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );1.297 - }1.298 + if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {1.299 + MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );1.300 +1.301 + uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );1.302 + uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );1.303 + // int dir = MMIO_READ( EXTDMA, IDEDMADIR );1.304 +1.305 + uint32_t xfer = ide_read_data_dma( addr, length );1.306 + MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );1.307 + MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );1.308 + } else { /* 0 */1.309 + MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );1.310 + }1.311 }1.312 }1.314 @@ -338,14 +338,14 @@1.315 unsigned char *data = alloca( count );1.316 uint32_t rcount = DMAC_get_buffer( 2, data, count );1.317 if( rcount != count )1.318 - WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );1.319 -1.320 + WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );1.321 +1.322 pvr2_dma_write( destaddr, data, rcount );1.323 -1.324 +1.325 MMIO_WRITE( ASIC, PVRDMACTL, 0 );1.326 MMIO_WRITE( ASIC, PVRDMACNT, 0 );1.327 if( destaddr & 0x01000000 ) { /* Write to texture RAM */1.328 - MMIO_WRITE( ASIC, PVRDMADEST, destaddr + rcount );1.329 + MMIO_WRITE( ASIC, PVRDMADEST, destaddr + rcount );1.330 }1.331 asic_event( EVENT_PVR_DMA );1.332 }1.333 @@ -356,7 +356,7 @@1.334 sh4addr_t data_addr = MMIO_READ( ASIC, SORTDMADATA );1.335 int table_size = MMIO_READ( ASIC, SORTDMATSIZ );1.336 int data_size = MMIO_READ( ASIC, SORTDMADSIZ );1.337 -1.338 +1.339 WARN( "Sort DMA not implemented" );1.340 }1.342 @@ -364,21 +364,21 @@1.343 {1.344 switch( reg ) {1.345 case PIRQ1:1.346 - break; /* Treat this as read-only for the moment */1.347 + break; /* Treat this as read-only for the moment */1.348 case PIRQ0:1.349 - val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */1.350 - MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );1.351 - asic_check_cleared_events();1.352 - break;1.353 + val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */1.354 + MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );1.355 + asic_check_cleared_events();1.356 + break;1.357 case PIRQ2:1.358 - /* Clear any events */1.359 - val = MMIO_READ(ASIC, reg)&(~val);1.360 - MMIO_WRITE( ASIC, reg, val );1.361 - if( val == 0 ) { /* all clear - clear the cascade bit */1.362 - MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );1.363 - }1.364 - asic_check_cleared_events();1.365 - break;1.366 + /* Clear any events */1.367 + val = MMIO_READ(ASIC, reg)&(~val);1.368 + MMIO_WRITE( ASIC, reg, val );1.369 + if( val == 0 ) { /* all clear - clear the cascade bit */1.370 + MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );1.371 + }1.372 + asic_check_cleared_events();1.373 + break;1.374 case IRQA0:1.375 case IRQA1:1.376 case IRQA2:1.377 @@ -388,37 +388,37 @@1.378 case IRQC0:1.379 case IRQC1:1.380 case IRQC2:1.381 - MMIO_WRITE( ASIC, reg, val );1.382 - asic_event_mask_changed();1.383 - break;1.384 + MMIO_WRITE( ASIC, reg, val );1.385 + asic_event_mask_changed();1.386 + break;1.387 case SYSRESET:1.388 - if( val == 0x7611 ) {1.389 - dreamcast_reset();1.390 - } else {1.391 - WARN( "Unknown value %08X written to SYSRESET port", val );1.392 - }1.393 - break;1.394 + if( val == 0x7611 ) {1.395 + dreamcast_reset();1.396 + } else {1.397 + WARN( "Unknown value %08X written to SYSRESET port", val );1.398 + }1.399 + break;1.400 case MAPLE_STATE:1.401 - MMIO_WRITE( ASIC, reg, val );1.402 - if( val & 1 ) {1.403 - uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;1.404 - maple_handle_buffer( maple_addr );1.405 - MMIO_WRITE( ASIC, reg, 0 );1.406 - }1.407 - break;1.408 + MMIO_WRITE( ASIC, reg, val );1.409 + if( val & 1 ) {1.410 + uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;1.411 + maple_handle_buffer( maple_addr );1.412 + MMIO_WRITE( ASIC, reg, 0 );1.413 + }1.414 + break;1.415 case PVRDMADEST:1.416 - MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 );1.417 - break;1.418 + MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 );1.419 + break;1.420 case PVRDMACNT:1.421 - MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 );1.422 - break;1.423 + MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 );1.424 + break;1.425 case PVRDMACTL: /* Initiate PVR DMA transfer */1.426 - val = val & 0x01;1.427 - MMIO_WRITE( ASIC, reg, val );1.428 - if( val == 1 ) {1.429 - pvr_dma_transfer();1.430 - }1.431 - break;1.432 + val = val & 0x01;1.433 + MMIO_WRITE( ASIC, reg, val );1.434 + if( val == 1 ) {1.435 + pvr_dma_transfer();1.436 + }1.437 + break;1.438 case SORTDMATBL: case SORTDMADATA:1.439 MMIO_WRITE( ASIC, reg, (val & 0x0FFFFFE0) | 0x08000000 );1.440 break;1.441 @@ -433,10 +433,10 @@1.442 }1.443 break;1.444 case MAPLE_DMA:1.445 - MMIO_WRITE( ASIC, reg, val );1.446 - break;1.447 + MMIO_WRITE( ASIC, reg, val );1.448 + break;1.449 default:1.450 - MMIO_WRITE( ASIC, reg, val );1.451 + MMIO_WRITE( ASIC, reg, val );1.452 }1.453 }1.455 @@ -457,136 +457,136 @@1.456 case IRQC1:1.457 case IRQC2:1.458 case MAPLE_STATE:1.459 - val = MMIO_READ(ASIC, reg);1.460 - return val;1.461 + val = MMIO_READ(ASIC, reg);1.462 + return val;1.463 case G2STATUS:1.464 - return g2_read_status();1.465 + return g2_read_status();1.466 default:1.467 - val = MMIO_READ(ASIC, reg);1.468 - return val;1.469 + val = MMIO_READ(ASIC, reg);1.470 + return val;1.471 }1.472 -1.473 +1.474 }1.476 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )1.477 {1.478 if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {1.479 - return; /* disabled */1.480 + return; /* disabled */1.481 }1.483 switch( reg ) {1.484 case IDEALTSTATUS: /* Device control */1.485 - ide_write_control( val );1.486 - break;1.487 + ide_write_control( val );1.488 + break;1.489 case IDEDATA:1.490 - ide_write_data_pio( val );1.491 - break;1.492 + ide_write_data_pio( val );1.493 + break;1.494 case IDEFEAT:1.495 - if( ide_can_write_regs() )1.496 - idereg.feature = (uint8_t)val;1.497 - break;1.498 + if( ide_can_write_regs() )1.499 + idereg.feature = (uint8_t)val;1.500 + break;1.501 case IDECOUNT:1.502 - if( ide_can_write_regs() )1.503 - idereg.count = (uint8_t)val;1.504 - break;1.505 + if( ide_can_write_regs() )1.506 + idereg.count = (uint8_t)val;1.507 + break;1.508 case IDELBA0:1.509 - if( ide_can_write_regs() )1.510 - idereg.lba0 = (uint8_t)val;1.511 - break;1.512 + if( ide_can_write_regs() )1.513 + idereg.lba0 = (uint8_t)val;1.514 + break;1.515 case IDELBA1:1.516 - if( ide_can_write_regs() )1.517 - idereg.lba1 = (uint8_t)val;1.518 - break;1.519 + if( ide_can_write_regs() )1.520 + idereg.lba1 = (uint8_t)val;1.521 + break;1.522 case IDELBA2:1.523 - if( ide_can_write_regs() )1.524 - idereg.lba2 = (uint8_t)val;1.525 - break;1.526 + if( ide_can_write_regs() )1.527 + idereg.lba2 = (uint8_t)val;1.528 + break;1.529 case IDEDEV:1.530 - if( ide_can_write_regs() )1.531 - idereg.device = (uint8_t)val;1.532 - break;1.533 + if( ide_can_write_regs() )1.534 + idereg.device = (uint8_t)val;1.535 + break;1.536 case IDECMD:1.537 - if( ide_can_write_regs() || val == IDE_CMD_NOP ) {1.538 - ide_write_command( (uint8_t)val );1.539 - }1.540 - break;1.541 + if( ide_can_write_regs() || val == IDE_CMD_NOP ) {1.542 + ide_write_command( (uint8_t)val );1.543 + }1.544 + break;1.545 case IDEDMASH4:1.546 - MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 );1.547 - break;1.548 + MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 );1.549 + break;1.550 case IDEDMASIZ:1.551 - MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );1.552 - break;1.553 + MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );1.554 + break;1.555 case IDEDMADIR:1.556 - MMIO_WRITE( EXTDMA, reg, val & 1 );1.557 - break;1.558 + MMIO_WRITE( EXTDMA, reg, val & 1 );1.559 + break;1.560 case IDEDMACTL1:1.561 case IDEDMACTL2:1.562 - MMIO_WRITE( EXTDMA, reg, val & 0x01 );1.563 - asic_ide_dma_transfer( );1.564 - break;1.565 + MMIO_WRITE( EXTDMA, reg, val & 0x01 );1.566 + asic_ide_dma_transfer( );1.567 + break;1.568 case IDEACTIVATE:1.569 - if( val == 0x001FFFFF ) {1.570 - idereg.interface_enabled = TRUE;1.571 - /* Conventional wisdom says that this is necessary but not1.572 - * sufficient to enable the IDE interface.1.573 - */1.574 - } else if( val == 0x000042FE ) {1.575 - idereg.interface_enabled = FALSE;1.576 - }1.577 - break;1.578 + if( val == 0x001FFFFF ) {1.579 + idereg.interface_enabled = TRUE;1.580 + /* Conventional wisdom says that this is necessary but not1.581 + * sufficient to enable the IDE interface.1.582 + */1.583 + } else if( val == 0x000042FE ) {1.584 + idereg.interface_enabled = FALSE;1.585 + }1.586 + break;1.587 case G2DMA0EXT: case G2DMA0SH4: case G2DMA0SIZ:1.588 case G2DMA1EXT: case G2DMA1SH4: case G2DMA1SIZ:1.589 case G2DMA2EXT: case G2DMA2SH4: case G2DMA2SIZ:1.590 case G2DMA3EXT: case G2DMA3SH4: case G2DMA3SIZ:1.591 - MMIO_WRITE( EXTDMA, reg, val & 0x9FFFFFE0 );1.592 - break;1.593 + MMIO_WRITE( EXTDMA, reg, val & 0x9FFFFFE0 );1.594 + break;1.595 case G2DMA0MOD: case G2DMA1MOD: case G2DMA2MOD: case G2DMA3MOD:1.596 - MMIO_WRITE( EXTDMA, reg, val & 0x07 );1.597 - break;1.598 + MMIO_WRITE( EXTDMA, reg, val & 0x07 );1.599 + break;1.600 case G2DMA0DIR: case G2DMA1DIR: case G2DMA2DIR: case G2DMA3DIR:1.601 - MMIO_WRITE( EXTDMA, reg, val & 0x01 );1.602 - break;1.603 + MMIO_WRITE( EXTDMA, reg, val & 0x01 );1.604 + break;1.605 case G2DMA0CTL1:1.606 case G2DMA0CTL2:1.607 - MMIO_WRITE( EXTDMA, reg, val & 1);1.608 - g2_dma_transfer( 0 );1.609 - break;1.610 + MMIO_WRITE( EXTDMA, reg, val & 1);1.611 + g2_dma_transfer( 0 );1.612 + break;1.613 case G2DMA0STOP:1.614 - MMIO_WRITE( EXTDMA, reg, val & 0x37 );1.615 - break;1.616 + MMIO_WRITE( EXTDMA, reg, val & 0x37 );1.617 + break;1.618 case G2DMA1CTL1:1.619 case G2DMA1CTL2:1.620 - MMIO_WRITE( EXTDMA, reg, val & 1);1.621 - g2_dma_transfer( 1 );1.622 - break;1.623 + MMIO_WRITE( EXTDMA, reg, val & 1);1.624 + g2_dma_transfer( 1 );1.625 + break;1.627 case G2DMA1STOP:1.628 - MMIO_WRITE( EXTDMA, reg, val & 0x37 );1.629 - break;1.630 + MMIO_WRITE( EXTDMA, reg, val & 0x37 );1.631 + break;1.632 case G2DMA2CTL1:1.633 case G2DMA2CTL2:1.634 - MMIO_WRITE( EXTDMA, reg, val &1 );1.635 - g2_dma_transfer( 2 );1.636 - break;1.637 + MMIO_WRITE( EXTDMA, reg, val &1 );1.638 + g2_dma_transfer( 2 );1.639 + break;1.640 case G2DMA2STOP:1.641 - MMIO_WRITE( EXTDMA, reg, val & 0x37 );1.642 - break;1.643 + MMIO_WRITE( EXTDMA, reg, val & 0x37 );1.644 + break;1.645 case G2DMA3CTL1:1.646 case G2DMA3CTL2:1.647 - MMIO_WRITE( EXTDMA, reg, val &1 );1.648 - g2_dma_transfer( 3 );1.649 - break;1.650 + MMIO_WRITE( EXTDMA, reg, val &1 );1.651 + g2_dma_transfer( 3 );1.652 + break;1.653 case G2DMA3STOP:1.654 - MMIO_WRITE( EXTDMA, reg, val & 0x37 );1.655 - break;1.656 + MMIO_WRITE( EXTDMA, reg, val & 0x37 );1.657 + break;1.658 case PVRDMA2CTL1:1.659 case PVRDMA2CTL2:1.660 - if( val != 0 ) {1.661 - ERROR( "Write to unimplemented DMA control register %08X", reg );1.662 - }1.663 - break;1.664 + if( val != 0 ) {1.665 + ERROR( "Write to unimplemented DMA control register %08X", reg );1.666 + }1.667 + break;1.668 default:1.669 - MMIO_WRITE( EXTDMA, reg, val );1.670 + MMIO_WRITE( EXTDMA, reg, val );1.671 }1.672 }1.674 @@ -594,13 +594,13 @@1.675 {1.676 uint32_t val;1.677 if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {1.678 - return 0xFFFFFFFF; /* disabled */1.679 + return 0xFFFFFFFF; /* disabled */1.680 }1.682 switch( reg ) {1.683 case IDEALTSTATUS:1.684 - val = idereg.status;1.685 - return val;1.686 + val = idereg.status;1.687 + return val;1.688 case IDEDATA: return ide_read_data_pio( );1.689 case IDEFEAT: return idereg.error;1.690 case IDECOUNT:return idereg.count;1.691 @@ -609,11 +609,11 @@1.692 case IDELBA2: return idereg.lba2;1.693 case IDEDEV: return idereg.device;1.694 case IDECMD:1.695 - val = ide_read_status();1.696 - return val;1.697 + val = ide_read_status();1.698 + return val;1.699 default:1.700 - val = MMIO_READ( EXTDMA, reg );1.701 - return val;1.702 + val = MMIO_READ( EXTDMA, reg );1.703 + return val;1.704 }1.705 }
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