filename | src/sh4/sh4core.h |
changeset | 265:5daf59b7f31b |
prev | 260:c82e26ec0cac |
next | 302:96b5cc24309c |
author | nkeynes |
date | Sat Jan 06 04:06:36 2007 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Implement event queue. Fix pvr2 timing (yes, again). |
file | annotate | diff | log | raw |
1.1 --- a/src/sh4/sh4core.h Wed Jan 03 09:00:17 2007 +00001.2 +++ b/src/sh4/sh4core.h Sat Jan 06 04:06:36 2007 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: sh4core.h,v 1.15 2007-01-03 09:00:17 nkeynes Exp $1.6 + * $Id: sh4core.h,v 1.16 2007-01-06 04:06:36 nkeynes Exp $1.7 *1.8 * This file defines the internal functions exported/used by the SH4 core,1.9 * except for disassembly functions defined in sh4dasm.h1.10 @@ -53,6 +53,9 @@1.11 */1.12 #define SH4_STATE_STANDBY 41.14 +#define PENDING_IRQ 11.15 +#define PENDING_EVENT 21.16 +1.17 struct sh4_registers {1.18 uint32_t r[16];1.19 uint32_t r_bank[8]; /* hidden banked registers */1.20 @@ -67,7 +70,9 @@1.22 uint32_t new_pc; /* Not a real register, but used to handle delay slots */1.23 uint32_t icount; /* Also not a real register, instruction counter */1.24 - uint32_t int_pending; /* flag set by the INTC = pending priority level */1.25 + uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF1.26 + when no events are pending */1.27 + uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */1.28 int in_delay_slot; /* flag to indicate the current instruction is in1.29 * a delay slot (certain rules apply) */1.30 uint32_t slice_cycle; /* Current cycle within the timeslice */1.31 @@ -147,7 +152,7 @@1.33 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)1.34 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)1.35 -#define SH4_INT_PENDING() (sh4r.int_pending && !sh4r.in_delay_slot)1.36 +#define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)1.38 #define FPSCR_FR 0x00200000 /* FPU register bank */1.39 #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
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