1.1 --- a/src/pvr2/tacore.c	Thu Aug 07 23:32:34 2008 +0000
     1.2 +++ b/src/pvr2/tacore.c	Wed Mar 04 23:12:21 2009 +0000
     1.3 @@ -119,8 +119,7 @@
     1.4  
     1.5  #define TILESLOT( x, y ) (ta_status.current_tile_matrix + (ta_status.current_tile_size * (y * ta_status.width+ x) << 2))
     1.6  
     1.7 -extern char *video_base;
     1.8 -#define PVRRAM(addr) (*(uint32_t *)(video_base + ((addr)&PVR2_RAM_MASK)))
     1.9 +#define PVRRAM(addr) (*(uint32_t *)(pvr2_main_ram + ((addr)&PVR2_RAM_MASK)))
    1.10  
    1.11  struct pvr2_ta_vertex {
    1.12      float x,y,z;
    1.13 @@ -296,7 +295,7 @@
    1.14  
    1.15          /* Initialize each tile to 0xF0000000 */
    1.16          if( ta_status.current_tile_size != 0 ) {
    1.17 -            p = (uint32_t *)(video_base + ta_status.current_tile_matrix);
    1.18 +            p = (uint32_t *)(pvr2_main_ram + ta_status.current_tile_matrix);
    1.19              for( i=0; i< ta_status.width * ta_status.height; i++ ) {
    1.20                  *p = 0xF0000000;
    1.21                  p += ta_status.current_tile_size;
    1.22 @@ -346,7 +345,7 @@
    1.23      int rv;
    1.24      int posn = MMIO_READ( PVR2, TA_POLYPOS );
    1.25      int end = MMIO_READ( PVR2, TA_POLYEND );
    1.26 -    uint32_t *target = (uint32_t *)(video_base + posn);
    1.27 +    uint32_t *target = (uint32_t *)(pvr2_main_ram + posn);
    1.28      for( rv=0; rv < length; rv++ ) {
    1.29          if( posn == end ) {
    1.30              asic_event( EVENT_PVR_PRIM_ALLOC_FAIL );
    1.31 @@ -1200,3 +1199,11 @@
    1.32          buf += 32;
    1.33      }
    1.34  }
    1.35 +
    1.36 +void FASTCALL pvr2_ta_write_burst( sh4addr_t addr, unsigned char *data )
    1.37 +{
    1.38 +    if( ta_status.debug_output ) {
    1.39 +        fwrite_dump32( (uint32_t *)data, 32, stderr );
    1.40 +    }
    1.41 +    pvr2_ta_process_block( data );
    1.42 +}