filename | src/sh4/sh4x86.in |
changeset | 991:60c7fab9c880 |
prev | 975:007bf7eb944f |
next | 992:7c15f8a71995 |
author | nkeynes |
date | Wed Mar 04 23:12:21 2009 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Move xltcache to xlat/ src directory Commit new and improved x86 opcode file - cleaned up and added support for amd64 extended registers |
file | annotate | diff | log | raw |
1.1 --- a/src/sh4/sh4x86.in Mon Jan 26 07:26:24 2009 +00001.2 +++ b/src/sh4/sh4x86.in Wed Mar 04 23:12:21 2009 +00001.3 @@ -26,17 +26,39 @@1.4 #endif1.6 #include "lxdream.h"1.7 -#include "sh4/xltcache.h"1.8 #include "sh4/sh4core.h"1.9 #include "sh4/sh4trans.h"1.10 #include "sh4/sh4stat.h"1.11 #include "sh4/sh4mmio.h"1.12 -#include "sh4/x86op.h"1.13 #include "sh4/mmu.h"1.14 +#include "xlat/xltcache.h"1.15 +#include "xlat/x86/x86op.h"1.16 #include "clock.h"1.18 #define DEFAULT_BACKPATCH_SIZE 40961.20 +/* Offset of a reg relative to the sh4r structure */1.21 +#define REG_OFFSET(reg) (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)1.22 +1.23 +#define R_T REG_OFFSET(t)1.24 +#define R_Q REG_OFFSET(q)1.25 +#define R_S REG_OFFSET(s)1.26 +#define R_M REG_OFFSET(m)1.27 +#define R_SR REG_OFFSET(sr)1.28 +#define R_GBR REG_OFFSET(gbr)1.29 +#define R_SSR REG_OFFSET(ssr)1.30 +#define R_SPC REG_OFFSET(spc)1.31 +#define R_VBR REG_OFFSET(vbr)1.32 +#define R_MACH REG_OFFSET(mac)+41.33 +#define R_MACL REG_OFFSET(mac)1.34 +#define R_PC REG_OFFSET(pc)1.35 +#define R_NEW_PC REG_OFFSET(new_pc)1.36 +#define R_PR REG_OFFSET(pr)1.37 +#define R_SGR REG_OFFSET(sgr)1.38 +#define R_FPUL REG_OFFSET(fpul)1.39 +#define R_FPSCR REG_OFFSET(fpscr)1.40 +#define R_DBR REG_OFFSET(dbr)1.41 +1.42 struct backpatch_record {1.43 uint32_t fixup_offset;1.44 uint32_t fixup_icount;1.45 @@ -72,32 +94,6 @@1.46 uint32_t backpatch_size;1.47 };1.49 -#define TSTATE_NONE -11.50 -#define TSTATE_O 01.51 -#define TSTATE_C 21.52 -#define TSTATE_E 41.53 -#define TSTATE_NE 51.54 -#define TSTATE_G 0xF1.55 -#define TSTATE_GE 0xD1.56 -#define TSTATE_A 71.57 -#define TSTATE_AE 31.58 -1.59 -#ifdef ENABLE_SH4STATS1.60 -#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE1.61 -#else1.62 -#define COUNT_INST(id)1.63 -#endif1.64 -1.65 -/** Branch if T is set (either in the current cflags, or in sh4r.t) */1.66 -#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \1.67 - CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \1.68 - OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)1.69 -1.70 -/** Branch if T is clear (either in the current cflags or in sh4r.t) */1.71 -#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \1.72 - CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \1.73 - OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)1.74 -1.75 static struct sh4_x86_state sh4_x86;1.77 static uint32_t max_int = 0x7FFFFFFF;1.78 @@ -125,6 +121,12 @@1.80 static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )1.81 {1.82 + int reloc_size = 4;1.83 +1.84 + if( exc_code == -2 ) {1.85 + reloc_size = sizeof(void *);1.86 + }1.87 +1.88 if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {1.89 sh4_x86.backpatch_size <<= 1;1.90 sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list,1.91 @@ -134,106 +136,107 @@1.92 if( sh4_x86.in_delay_slot ) {1.93 fixup_pc -= 2;1.94 }1.95 +1.96 sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset =1.97 - ((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);1.98 + (((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;1.99 sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;1.100 sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;1.101 sh4_x86.backpatch_posn++;1.102 }1.104 -/**1.105 - * Emit an instruction to load an SH4 reg into a real register1.106 - */1.107 -static inline void load_reg( int x86reg, int sh4reg )1.108 -{1.109 - /* mov [bp+n], reg */1.110 - OP(0x8B);1.111 - OP(0x45 + (x86reg<<3));1.112 - OP(REG_OFFSET(r[sh4reg]));1.113 -}1.114 +#define TSTATE_NONE -11.115 +#define TSTATE_O 01.116 +#define TSTATE_C 21.117 +#define TSTATE_E 41.118 +#define TSTATE_NE 51.119 +#define TSTATE_G 0xF1.120 +#define TSTATE_GE 0xD1.121 +#define TSTATE_A 71.122 +#define TSTATE_AE 31.124 -static inline void load_reg16s( int x86reg, int sh4reg )1.125 -{1.126 - OP(0x0F);1.127 - OP(0xBF);1.128 - MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));1.129 -}1.130 +#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)1.131 +#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)1.133 -static inline void load_reg16u( int x86reg, int sh4reg )1.134 -{1.135 - OP(0x0F);1.136 - OP(0xB7);1.137 - MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));1.138 +/* Convenience instructions */1.139 +#define LDC_t() CMPB_imms_rbpdisp(1,R_T); CMC()1.140 +#define SETE_t() SETCCB_cc_rbpdisp(X86_COND_E,R_T)1.141 +#define SETA_t() SETCCB_cc_rbpdisp(X86_COND_A,R_T)1.142 +#define SETAE_t() SETCCB_cc_rbpdisp(X86_COND_AE,R_T)1.143 +#define SETG_t() SETCCB_cc_rbpdisp(X86_COND_G,R_T)1.144 +#define SETGE_t() SETCCB_cc_rbpdisp(X86_COND_GE,R_T)1.145 +#define SETC_t() SETCCB_cc_rbpdisp(X86_COND_C,R_T)1.146 +#define SETO_t() SETCCB_cc_rbpdisp(X86_COND_O,R_T)1.147 +#define SETNE_t() SETCCB_cc_rbpdisp(X86_COND_NE,R_T)1.148 +#define SETC_r8(r1) SETCCB_cc_r8(X86_COND_C, r1)1.149 +#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)1.150 +#define JE_label(label) JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)1.151 +#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)1.152 +#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)1.153 +#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)1.154 +#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)1.155 +#define JS_label(label) JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)1.156 +#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)1.157 +#define JNE_exc(exc) JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)1.159 -}1.160 +/** Branch if T is set (either in the current cflags, or in sh4r.t) */1.161 +#define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \1.162 + CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \1.163 + JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)1.165 -#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )1.166 -#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )1.167 -/**1.168 - * Emit an instruction to load an immediate value into a register1.169 - */1.170 -static inline void load_imm32( int x86reg, uint32_t value ) {1.171 - /* mov #value, reg */1.172 - OP(0xB8 + x86reg);1.173 - OP32(value);1.174 -}1.175 +/** Branch if T is clear (either in the current cflags or in sh4r.t) */1.176 +#define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \1.177 + CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \1.178 + JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)1.180 -1.181 -/**1.182 - * Load an immediate 64-bit quantity (note: x86-64 only)1.183 - */1.184 -static inline void load_imm64( int x86reg, uint64_t value ) {1.185 - /* mov #value, reg */1.186 - REXW();1.187 - OP(0xB8 + x86reg);1.188 - OP64(value);1.189 -}1.190 -1.191 -/**1.192 - * Emit an instruction to store an SH4 reg (RN)1.193 - */1.194 -void static inline store_reg( int x86reg, int sh4reg ) {1.195 - /* mov reg, [bp+n] */1.196 - OP(0x89);1.197 - OP(0x45 + (x86reg<<3));1.198 - OP(REG_OFFSET(r[sh4reg]));1.199 -}1.200 +#define load_reg16s(x86reg,sh4reg) MOVSXL_rbpdisp16_r32( REG_OFFSET(r[sh4reg]), x86reg )1.201 +#define load_reg16u(x86reg,sh4reg) MOVZXL_rbpdisp16_r32( REG_OFFSET(r[sh4reg]), x86reg )1.202 +#define load_imm32(x86reg,value) MOVL_imm32_r32(value,x86reg)1.203 +#define load_imm64(x86reg,value) MOVQ_imm64_r64(value,x86reg)1.204 +#define load_reg(x86reg,sh4reg) MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )1.205 +#define store_reg(x86reg,sh4reg) MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )1.206 +#define load_spreg(x86reg, regoff) MOVL_rbpdisp_r32( regoff, x86reg )1.207 +#define store_spreg(x86reg, regoff) MOVL_r32_rbpdisp( x86reg, regoff )1.209 /**1.210 * Load an FR register (single-precision floating point) into an integer x861.211 * register (eg for register-to-register moves)1.212 */1.213 -#define load_fr(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )1.214 -#define load_xf(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )1.215 +#define load_fr(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )1.216 +#define load_xf(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )1.218 /**1.219 * Load the low half of a DR register (DR or XD) into an integer x86 register1.220 */1.221 -#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )1.222 -#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )1.223 +#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )1.224 +#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )1.226 /**1.227 * Store an FR register (single-precision floating point) from an integer x86+1.228 * register (eg for register-to-register moves)1.229 */1.230 -#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )1.231 -#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )1.232 +#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )1.233 +#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )1.235 -#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )1.236 -#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )1.237 +#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )1.238 +#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )1.241 -#define push_fpul() FLDF_sh4r(R_FPUL)1.242 -#define pop_fpul() FSTPF_sh4r(R_FPUL)1.243 -#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )1.244 -#define pop_fr(frm) FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )1.245 -#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )1.246 -#define pop_xf(frm) FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )1.247 -#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )1.248 -#define pop_dr(frm) FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )1.249 -#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )1.250 -#define pop_xdr(frm) FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )1.251 +#define push_fpul() FLDF_rbpdisp(R_FPUL)1.252 +#define pop_fpul() FSTPF_rbpdisp(R_FPUL)1.253 +#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )1.254 +#define pop_fr(frm) FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )1.255 +#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )1.256 +#define pop_xf(frm) FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )1.257 +#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )1.258 +#define pop_dr(frm) FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )1.259 +#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )1.260 +#define pop_xdr(frm) FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )1.262 +#ifdef ENABLE_SH4STATS1.263 +#define COUNT_INST(id) load_imm32(REG_EAX,id); call_func1(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE1.264 +#else1.265 +#define COUNT_INST(id)1.266 +#endif1.269 /* Exception checks - Note that all exception checks will clobber EAX */1.270 @@ -253,8 +256,8 @@1.271 #define check_fpuen( ) \1.272 if( !sh4_x86.fpuen_checked ) {\1.273 sh4_x86.fpuen_checked = TRUE;\1.274 - load_spreg( R_EAX, R_SR );\1.275 - AND_imm32_r32( SR_FD, R_EAX );\1.276 + load_spreg( REG_EAX, R_SR );\1.277 + ANDL_imms_r32( SR_FD, REG_EAX );\1.278 if( sh4_x86.in_delay_slot ) {\1.279 JNE_exc(EXC_SLOT_FPU_DISABLED);\1.280 } else {\1.281 @@ -264,46 +267,46 @@1.282 }1.284 #define check_ralign16( x86reg ) \1.285 - TEST_imm32_r32( 0x00000001, x86reg ); \1.286 + TESTL_imms_r32( 0x00000001, x86reg ); \1.287 JNE_exc(EXC_DATA_ADDR_READ)1.289 #define check_walign16( x86reg ) \1.290 - TEST_imm32_r32( 0x00000001, x86reg ); \1.291 + TESTL_imms_r32( 0x00000001, x86reg ); \1.292 JNE_exc(EXC_DATA_ADDR_WRITE);1.294 #define check_ralign32( x86reg ) \1.295 - TEST_imm32_r32( 0x00000003, x86reg ); \1.296 + TESTL_imms_r32( 0x00000003, x86reg ); \1.297 JNE_exc(EXC_DATA_ADDR_READ)1.299 #define check_walign32( x86reg ) \1.300 - TEST_imm32_r32( 0x00000003, x86reg ); \1.301 + TESTL_imms_r32( 0x00000003, x86reg ); \1.302 JNE_exc(EXC_DATA_ADDR_WRITE);1.304 #define check_ralign64( x86reg ) \1.305 - TEST_imm32_r32( 0x00000007, x86reg ); \1.306 + TESTL_imms_r32( 0x00000007, x86reg ); \1.307 JNE_exc(EXC_DATA_ADDR_READ)1.309 #define check_walign64( x86reg ) \1.310 - TEST_imm32_r32( 0x00000007, x86reg ); \1.311 + TESTL_imms_r32( 0x00000007, x86reg ); \1.312 JNE_exc(EXC_DATA_ADDR_WRITE);1.314 #define UNDEF(ir)1.315 #define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )1.316 -#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }1.317 +#define MEM_RESULT(value_reg) if(value_reg != REG_EAX) { MOVL_r32_r32(REG_EAX,value_reg); }1.318 /* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so1.319 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.1.320 */1.322 #ifdef HAVE_FRAME_ADDRESS1.323 #define _CALL_READ(addr_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \1.324 - call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \1.325 - call_func1_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, pc); }1.326 + call_func1_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \1.327 + call_func1_r32disp8_exc(REG_ECX, MEM_REGION_PTR(fn), addr_reg, pc); }1.328 #define _CALL_WRITE(addr_reg, val_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \1.329 - call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \1.330 - call_func2_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); }1.331 + call_func2_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \1.332 + call_func2_r32disp8_exc(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); }1.333 #else1.334 -#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg)1.335 -#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg)1.336 +#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg)1.337 +#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg)1.338 #endif1.340 #define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte); MEM_RESULT(value_reg)1.341 @@ -354,8 +357,8 @@1.342 */1.343 void sh4_translate_emit_breakpoint( sh4vma_t pc )1.344 {1.345 - load_imm32( R_EAX, pc );1.346 - call_func1( sh4_translate_breakpoint_hit, R_EAX );1.347 + load_imm32( REG_EAX, pc );1.348 + call_func1( sh4_translate_breakpoint_hit, REG_EAX );1.349 sh4_x86.tstate = TSTATE_NONE;1.350 }1.352 @@ -376,20 +379,20 @@1.353 */1.354 void exit_block_emu( sh4vma_t endpc )1.355 {1.356 - load_imm32( R_ECX, endpc - sh4_x86.block_start_pc ); // 51.357 - ADD_r32_sh4r( R_ECX, R_PC );1.358 + load_imm32( REG_ECX, endpc - sh4_x86.block_start_pc ); // 51.359 + ADDL_r32_rbpdisp( REG_ECX, R_PC );1.361 - load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 51.362 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 61.363 - load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );1.364 - store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );1.365 + load_imm32( REG_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 51.366 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 61.367 + load_imm32( REG_ECX, sh4_x86.in_delay_slot ? 1 : 0 );1.368 + store_spreg( REG_ECX, REG_OFFSET(in_delay_slot) );1.370 call_func0( sh4_execute_instruction );1.371 - load_spreg( R_EAX, R_PC );1.372 + load_spreg( REG_EAX, R_PC );1.373 if( sh4_x86.tlb_on ) {1.374 - call_func1(xlat_get_code_by_vma,R_EAX);1.375 + call_func1(xlat_get_code_by_vma,REG_EAX);1.376 } else {1.377 - call_func1(xlat_get_code,R_EAX);1.378 + call_func1(xlat_get_code,REG_EAX);1.379 }1.380 exit_block();1.381 }1.382 @@ -417,15 +420,15 @@1.383 /* ALU operations */1.384 ADD Rm, Rn {:1.385 COUNT_INST(I_ADD);1.386 - load_reg( R_EAX, Rm );1.387 - load_reg( R_ECX, Rn );1.388 - ADD_r32_r32( R_EAX, R_ECX );1.389 - store_reg( R_ECX, Rn );1.390 + load_reg( REG_EAX, Rm );1.391 + load_reg( REG_ECX, Rn );1.392 + ADDL_r32_r32( REG_EAX, REG_ECX );1.393 + store_reg( REG_ECX, Rn );1.394 sh4_x86.tstate = TSTATE_NONE;1.395 :}1.396 ADD #imm, Rn {:1.397 COUNT_INST(I_ADDI);1.398 - ADD_imm8s_sh4r( imm, REG_OFFSET(r[Rn]) );1.399 + ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );1.400 sh4_x86.tstate = TSTATE_NONE;1.401 :}1.402 ADDC Rm, Rn {:1.403 @@ -433,122 +436,122 @@1.404 if( sh4_x86.tstate != TSTATE_C ) {1.405 LDC_t();1.406 }1.407 - load_reg( R_EAX, Rm );1.408 - load_reg( R_ECX, Rn );1.409 - ADC_r32_r32( R_EAX, R_ECX );1.410 - store_reg( R_ECX, Rn );1.411 + load_reg( REG_EAX, Rm );1.412 + load_reg( REG_ECX, Rn );1.413 + ADCL_r32_r32( REG_EAX, REG_ECX );1.414 + store_reg( REG_ECX, Rn );1.415 SETC_t();1.416 sh4_x86.tstate = TSTATE_C;1.417 :}1.418 ADDV Rm, Rn {:1.419 COUNT_INST(I_ADDV);1.420 - load_reg( R_EAX, Rm );1.421 - load_reg( R_ECX, Rn );1.422 - ADD_r32_r32( R_EAX, R_ECX );1.423 - store_reg( R_ECX, Rn );1.424 + load_reg( REG_EAX, Rm );1.425 + load_reg( REG_ECX, Rn );1.426 + ADDL_r32_r32( REG_EAX, REG_ECX );1.427 + store_reg( REG_ECX, Rn );1.428 SETO_t();1.429 sh4_x86.tstate = TSTATE_O;1.430 :}1.431 AND Rm, Rn {:1.432 COUNT_INST(I_AND);1.433 - load_reg( R_EAX, Rm );1.434 - load_reg( R_ECX, Rn );1.435 - AND_r32_r32( R_EAX, R_ECX );1.436 - store_reg( R_ECX, Rn );1.437 + load_reg( REG_EAX, Rm );1.438 + load_reg( REG_ECX, Rn );1.439 + ANDL_r32_r32( REG_EAX, REG_ECX );1.440 + store_reg( REG_ECX, Rn );1.441 sh4_x86.tstate = TSTATE_NONE;1.442 :}1.443 AND #imm, R0 {:1.444 COUNT_INST(I_ANDI);1.445 - load_reg( R_EAX, 0 );1.446 - AND_imm32_r32(imm, R_EAX);1.447 - store_reg( R_EAX, 0 );1.448 + load_reg( REG_EAX, 0 );1.449 + ANDL_imms_r32(imm, REG_EAX);1.450 + store_reg( REG_EAX, 0 );1.451 sh4_x86.tstate = TSTATE_NONE;1.452 :}1.453 AND.B #imm, @(R0, GBR) {:1.454 COUNT_INST(I_ANDB);1.455 - load_reg( R_EAX, 0 );1.456 - ADD_sh4r_r32( R_GBR, R_EAX );1.457 - MOV_r32_esp8(R_EAX, 0);1.458 - MEM_READ_BYTE_FOR_WRITE( R_EAX, R_EDX );1.459 - MOV_esp8_r32(0, R_EAX);1.460 - AND_imm32_r32(imm, R_EDX );1.461 - MEM_WRITE_BYTE( R_EAX, R_EDX );1.462 + load_reg( REG_EAX, 0 );1.463 + ADDL_rbpdisp_r32( R_GBR, REG_EAX );1.464 + MOVL_r32_rspdisp(REG_EAX, 0);1.465 + MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );1.466 + MOVL_rspdisp_r32(0, REG_EAX);1.467 + ANDL_imms_r32(imm, REG_EDX );1.468 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );1.469 sh4_x86.tstate = TSTATE_NONE;1.470 :}1.471 CMP/EQ Rm, Rn {:1.472 COUNT_INST(I_CMPEQ);1.473 - load_reg( R_EAX, Rm );1.474 - load_reg( R_ECX, Rn );1.475 - CMP_r32_r32( R_EAX, R_ECX );1.476 + load_reg( REG_EAX, Rm );1.477 + load_reg( REG_ECX, Rn );1.478 + CMPL_r32_r32( REG_EAX, REG_ECX );1.479 SETE_t();1.480 sh4_x86.tstate = TSTATE_E;1.481 :}1.482 CMP/EQ #imm, R0 {:1.483 COUNT_INST(I_CMPEQI);1.484 - load_reg( R_EAX, 0 );1.485 - CMP_imm8s_r32(imm, R_EAX);1.486 + load_reg( REG_EAX, 0 );1.487 + CMPL_imms_r32(imm, REG_EAX);1.488 SETE_t();1.489 sh4_x86.tstate = TSTATE_E;1.490 :}1.491 CMP/GE Rm, Rn {:1.492 COUNT_INST(I_CMPGE);1.493 - load_reg( R_EAX, Rm );1.494 - load_reg( R_ECX, Rn );1.495 - CMP_r32_r32( R_EAX, R_ECX );1.496 + load_reg( REG_EAX, Rm );1.497 + load_reg( REG_ECX, Rn );1.498 + CMPL_r32_r32( REG_EAX, REG_ECX );1.499 SETGE_t();1.500 sh4_x86.tstate = TSTATE_GE;1.501 :}1.502 CMP/GT Rm, Rn {:1.503 COUNT_INST(I_CMPGT);1.504 - load_reg( R_EAX, Rm );1.505 - load_reg( R_ECX, Rn );1.506 - CMP_r32_r32( R_EAX, R_ECX );1.507 + load_reg( REG_EAX, Rm );1.508 + load_reg( REG_ECX, Rn );1.509 + CMPL_r32_r32( REG_EAX, REG_ECX );1.510 SETG_t();1.511 sh4_x86.tstate = TSTATE_G;1.512 :}1.513 CMP/HI Rm, Rn {:1.514 COUNT_INST(I_CMPHI);1.515 - load_reg( R_EAX, Rm );1.516 - load_reg( R_ECX, Rn );1.517 - CMP_r32_r32( R_EAX, R_ECX );1.518 + load_reg( REG_EAX, Rm );1.519 + load_reg( REG_ECX, Rn );1.520 + CMPL_r32_r32( REG_EAX, REG_ECX );1.521 SETA_t();1.522 sh4_x86.tstate = TSTATE_A;1.523 :}1.524 CMP/HS Rm, Rn {:1.525 COUNT_INST(I_CMPHS);1.526 - load_reg( R_EAX, Rm );1.527 - load_reg( R_ECX, Rn );1.528 - CMP_r32_r32( R_EAX, R_ECX );1.529 + load_reg( REG_EAX, Rm );1.530 + load_reg( REG_ECX, Rn );1.531 + CMPL_r32_r32( REG_EAX, REG_ECX );1.532 SETAE_t();1.533 sh4_x86.tstate = TSTATE_AE;1.534 :}1.535 CMP/PL Rn {:1.536 COUNT_INST(I_CMPPL);1.537 - load_reg( R_EAX, Rn );1.538 - CMP_imm8s_r32( 0, R_EAX );1.539 + load_reg( REG_EAX, Rn );1.540 + CMPL_imms_r32( 0, REG_EAX );1.541 SETG_t();1.542 sh4_x86.tstate = TSTATE_G;1.543 :}1.544 CMP/PZ Rn {:1.545 COUNT_INST(I_CMPPZ);1.546 - load_reg( R_EAX, Rn );1.547 - CMP_imm8s_r32( 0, R_EAX );1.548 + load_reg( REG_EAX, Rn );1.549 + CMPL_imms_r32( 0, REG_EAX );1.550 SETGE_t();1.551 sh4_x86.tstate = TSTATE_GE;1.552 :}1.553 CMP/STR Rm, Rn {:1.554 COUNT_INST(I_CMPSTR);1.555 - load_reg( R_EAX, Rm );1.556 - load_reg( R_ECX, Rn );1.557 - XOR_r32_r32( R_ECX, R_EAX );1.558 - TEST_r8_r8( R_AL, R_AL );1.559 - JE_rel8(target1);1.560 - TEST_r8_r8( R_AH, R_AH );1.561 - JE_rel8(target2);1.562 - SHR_imm8_r32( 16, R_EAX );1.563 - TEST_r8_r8( R_AL, R_AL );1.564 - JE_rel8(target3);1.565 - TEST_r8_r8( R_AH, R_AH );1.566 + load_reg( REG_EAX, Rm );1.567 + load_reg( REG_ECX, Rn );1.568 + XORL_r32_r32( REG_ECX, REG_EAX );1.569 + TESTB_r8_r8( REG_AL, REG_AL );1.570 + JE_label(target1);1.571 + TESTB_r8_r8( REG_AH, REG_AH );1.572 + JE_label(target2);1.573 + SHRL_imm_r32( 16, REG_EAX );1.574 + TESTB_r8_r8( REG_AL, REG_AL );1.575 + JE_label(target3);1.576 + TESTB_r8_r8( REG_AH, REG_AH );1.577 JMP_TARGET(target1);1.578 JMP_TARGET(target2);1.579 JMP_TARGET(target3);1.580 @@ -557,130 +560,130 @@1.581 :}1.582 DIV0S Rm, Rn {:1.583 COUNT_INST(I_DIV0S);1.584 - load_reg( R_EAX, Rm );1.585 - load_reg( R_ECX, Rn );1.586 - SHR_imm8_r32( 31, R_EAX );1.587 - SHR_imm8_r32( 31, R_ECX );1.588 - store_spreg( R_EAX, R_M );1.589 - store_spreg( R_ECX, R_Q );1.590 - CMP_r32_r32( R_EAX, R_ECX );1.591 + load_reg( REG_EAX, Rm );1.592 + load_reg( REG_ECX, Rn );1.593 + SHRL_imm_r32( 31, REG_EAX );1.594 + SHRL_imm_r32( 31, REG_ECX );1.595 + store_spreg( REG_EAX, R_M );1.596 + store_spreg( REG_ECX, R_Q );1.597 + CMPL_r32_r32( REG_EAX, REG_ECX );1.598 SETNE_t();1.599 sh4_x86.tstate = TSTATE_NE;1.600 :}1.601 DIV0U {:1.602 COUNT_INST(I_DIV0U);1.603 - XOR_r32_r32( R_EAX, R_EAX );1.604 - store_spreg( R_EAX, R_Q );1.605 - store_spreg( R_EAX, R_M );1.606 - store_spreg( R_EAX, R_T );1.607 + XORL_r32_r32( REG_EAX, REG_EAX );1.608 + store_spreg( REG_EAX, R_Q );1.609 + store_spreg( REG_EAX, R_M );1.610 + store_spreg( REG_EAX, R_T );1.611 sh4_x86.tstate = TSTATE_C; // works for DIV11.612 :}1.613 DIV1 Rm, Rn {:1.614 COUNT_INST(I_DIV1);1.615 - load_spreg( R_ECX, R_M );1.616 - load_reg( R_EAX, Rn );1.617 + load_spreg( REG_ECX, R_M );1.618 + load_reg( REG_EAX, Rn );1.619 if( sh4_x86.tstate != TSTATE_C ) {1.620 LDC_t();1.621 }1.622 - RCL1_r32( R_EAX );1.623 - SETC_r8( R_DL ); // Q'1.624 - CMP_sh4r_r32( R_Q, R_ECX );1.625 - JE_rel8(mqequal);1.626 - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );1.627 - JMP_rel8(end);1.628 + RCLL_imm_r32( 1, REG_EAX );1.629 + SETC_r8( REG_DL ); // Q'1.630 + CMPL_rbpdisp_r32( R_Q, REG_ECX );1.631 + JE_label(mqequal);1.632 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );1.633 + JMP_label(end);1.634 JMP_TARGET(mqequal);1.635 - SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );1.636 + SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );1.637 JMP_TARGET(end);1.638 - store_reg( R_EAX, Rn ); // Done with Rn now1.639 - SETC_r8(R_AL); // tmp11.640 - XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp11.641 - XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M1.642 - store_spreg( R_ECX, R_Q );1.643 - XOR_imm8s_r32( 1, R_AL ); // T = !Q'1.644 - MOVZX_r8_r32( R_AL, R_EAX );1.645 - store_spreg( R_EAX, R_T );1.646 + store_reg( REG_EAX, Rn ); // Done with Rn now1.647 + SETC_r8(REG_AL); // tmp11.648 + XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp11.649 + XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M1.650 + store_spreg( REG_ECX, R_Q );1.651 + XORL_imms_r32( 1, REG_AL ); // T = !Q'1.652 + MOVZXL_r8_r32( REG_AL, REG_EAX );1.653 + store_spreg( REG_EAX, R_T );1.654 sh4_x86.tstate = TSTATE_NONE;1.655 :}1.656 DMULS.L Rm, Rn {:1.657 COUNT_INST(I_DMULS);1.658 - load_reg( R_EAX, Rm );1.659 - load_reg( R_ECX, Rn );1.660 - IMUL_r32(R_ECX);1.661 - store_spreg( R_EDX, R_MACH );1.662 - store_spreg( R_EAX, R_MACL );1.663 + load_reg( REG_EAX, Rm );1.664 + load_reg( REG_ECX, Rn );1.665 + IMULL_r32(REG_ECX);1.666 + store_spreg( REG_EDX, R_MACH );1.667 + store_spreg( REG_EAX, R_MACL );1.668 sh4_x86.tstate = TSTATE_NONE;1.669 :}1.670 DMULU.L Rm, Rn {:1.671 COUNT_INST(I_DMULU);1.672 - load_reg( R_EAX, Rm );1.673 - load_reg( R_ECX, Rn );1.674 - MUL_r32(R_ECX);1.675 - store_spreg( R_EDX, R_MACH );1.676 - store_spreg( R_EAX, R_MACL );1.677 + load_reg( REG_EAX, Rm );1.678 + load_reg( REG_ECX, Rn );1.679 + MULL_r32(REG_ECX);1.680 + store_spreg( REG_EDX, R_MACH );1.681 + store_spreg( REG_EAX, R_MACL );1.682 sh4_x86.tstate = TSTATE_NONE;1.683 :}1.684 DT Rn {:1.685 COUNT_INST(I_DT);1.686 - load_reg( R_EAX, Rn );1.687 - ADD_imm8s_r32( -1, R_EAX );1.688 - store_reg( R_EAX, Rn );1.689 + load_reg( REG_EAX, Rn );1.690 + ADDL_imms_r32( -1, REG_EAX );1.691 + store_reg( REG_EAX, Rn );1.692 SETE_t();1.693 sh4_x86.tstate = TSTATE_E;1.694 :}1.695 EXTS.B Rm, Rn {:1.696 COUNT_INST(I_EXTSB);1.697 - load_reg( R_EAX, Rm );1.698 - MOVSX_r8_r32( R_EAX, R_EAX );1.699 - store_reg( R_EAX, Rn );1.700 + load_reg( REG_EAX, Rm );1.701 + MOVSXL_r8_r32( REG_EAX, REG_EAX );1.702 + store_reg( REG_EAX, Rn );1.703 :}1.704 EXTS.W Rm, Rn {:1.705 COUNT_INST(I_EXTSW);1.706 - load_reg( R_EAX, Rm );1.707 - MOVSX_r16_r32( R_EAX, R_EAX );1.708 - store_reg( R_EAX, Rn );1.709 + load_reg( REG_EAX, Rm );1.710 + MOVSXL_r16_r32( REG_EAX, REG_EAX );1.711 + store_reg( REG_EAX, Rn );1.712 :}1.713 EXTU.B Rm, Rn {:1.714 COUNT_INST(I_EXTUB);1.715 - load_reg( R_EAX, Rm );1.716 - MOVZX_r8_r32( R_EAX, R_EAX );1.717 - store_reg( R_EAX, Rn );1.718 + load_reg( REG_EAX, Rm );1.719 + MOVZXL_r8_r32( REG_EAX, REG_EAX );1.720 + store_reg( REG_EAX, Rn );1.721 :}1.722 EXTU.W Rm, Rn {:1.723 COUNT_INST(I_EXTUW);1.724 - load_reg( R_EAX, Rm );1.725 - MOVZX_r16_r32( R_EAX, R_EAX );1.726 - store_reg( R_EAX, Rn );1.727 + load_reg( REG_EAX, Rm );1.728 + MOVZXL_r16_r32( REG_EAX, REG_EAX );1.729 + store_reg( REG_EAX, Rn );1.730 :}1.731 MAC.L @Rm+, @Rn+ {:1.732 COUNT_INST(I_MACL);1.733 if( Rm == Rn ) {1.734 - load_reg( R_EAX, Rm );1.735 - check_ralign32( R_EAX );1.736 - MEM_READ_LONG( R_EAX, R_EAX );1.737 - MOV_r32_esp8(R_EAX, 0);1.738 - load_reg( R_EAX, Rm );1.739 - LEA_r32disp8_r32( R_EAX, 4, R_EAX );1.740 - MEM_READ_LONG( R_EAX, R_EAX );1.741 - ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );1.742 + load_reg( REG_EAX, Rm );1.743 + check_ralign32( REG_EAX );1.744 + MEM_READ_LONG( REG_EAX, REG_EAX );1.745 + MOVL_r32_rspdisp(REG_EAX, 0);1.746 + load_reg( REG_EAX, Rm );1.747 + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );1.748 + MEM_READ_LONG( REG_EAX, REG_EAX );1.749 + ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );1.750 } else {1.751 - load_reg( R_EAX, Rm );1.752 - check_ralign32( R_EAX );1.753 - MEM_READ_LONG( R_EAX, R_EAX );1.754 - MOV_r32_esp8( R_EAX, 0 );1.755 - load_reg( R_EAX, Rn );1.756 - check_ralign32( R_EAX );1.757 - MEM_READ_LONG( R_EAX, R_EAX );1.758 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );1.759 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.760 + load_reg( REG_EAX, Rm );1.761 + check_ralign32( REG_EAX );1.762 + MEM_READ_LONG( REG_EAX, REG_EAX );1.763 + MOVL_r32_rspdisp( REG_EAX, 0 );1.764 + load_reg( REG_EAX, Rn );1.765 + check_ralign32( REG_EAX );1.766 + MEM_READ_LONG( REG_EAX, REG_EAX );1.767 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );1.768 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.769 }1.771 - IMUL_esp8( 0 );1.772 - ADD_r32_sh4r( R_EAX, R_MACL );1.773 - ADC_r32_sh4r( R_EDX, R_MACH );1.774 + IMULL_rspdisp( 0 );1.775 + ADDL_r32_rbpdisp( REG_EAX, R_MACL );1.776 + ADCL_r32_rbpdisp( REG_EDX, R_MACH );1.778 - load_spreg( R_ECX, R_S );1.779 - TEST_r32_r32(R_ECX, R_ECX);1.780 - JE_rel8( nosat );1.781 + load_spreg( REG_ECX, R_S );1.782 + TESTL_r32_r32(REG_ECX, REG_ECX);1.783 + JE_label( nosat );1.784 call_func0( signsat48 );1.785 JMP_TARGET( nosat );1.786 sh4_x86.tstate = TSTATE_NONE;1.787 @@ -688,49 +691,49 @@1.788 MAC.W @Rm+, @Rn+ {:1.789 COUNT_INST(I_MACW);1.790 if( Rm == Rn ) {1.791 - load_reg( R_EAX, Rm );1.792 - check_ralign16( R_EAX );1.793 - MEM_READ_WORD( R_EAX, R_EAX );1.794 - MOV_r32_esp8( R_EAX, 0 );1.795 - load_reg( R_EAX, Rm );1.796 - LEA_r32disp8_r32( R_EAX, 2, R_EAX );1.797 - MEM_READ_WORD( R_EAX, R_EAX );1.798 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );1.799 + load_reg( REG_EAX, Rm );1.800 + check_ralign16( REG_EAX );1.801 + MEM_READ_WORD( REG_EAX, REG_EAX );1.802 + MOVL_r32_rspdisp( REG_EAX, 0 );1.803 + load_reg( REG_EAX, Rm );1.804 + LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );1.805 + MEM_READ_WORD( REG_EAX, REG_EAX );1.806 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );1.807 // Note translate twice in case of page boundaries. Maybe worth1.808 // adding a page-boundary check to skip the second translation1.809 } else {1.810 - load_reg( R_EAX, Rm );1.811 - check_ralign16( R_EAX );1.812 - MEM_READ_WORD( R_EAX, R_EAX );1.813 - MOV_r32_esp8( R_EAX, 0 );1.814 - load_reg( R_EAX, Rn );1.815 - check_ralign16( R_EAX );1.816 - MEM_READ_WORD( R_EAX, R_EAX );1.817 - ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );1.818 - ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );1.819 + load_reg( REG_EAX, Rm );1.820 + check_ralign16( REG_EAX );1.821 + MEM_READ_WORD( REG_EAX, REG_EAX );1.822 + MOVL_r32_rspdisp( REG_EAX, 0 );1.823 + load_reg( REG_EAX, Rn );1.824 + check_ralign16( REG_EAX );1.825 + MEM_READ_WORD( REG_EAX, REG_EAX );1.826 + ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );1.827 + ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );1.828 }1.829 - IMUL_esp8( 0 );1.830 - load_spreg( R_ECX, R_S );1.831 - TEST_r32_r32( R_ECX, R_ECX );1.832 - JE_rel8( nosat );1.833 + IMULL_rspdisp( 0 );1.834 + load_spreg( REG_ECX, R_S );1.835 + TESTL_r32_r32( REG_ECX, REG_ECX );1.836 + JE_label( nosat );1.838 - ADD_r32_sh4r( R_EAX, R_MACL ); // 61.839 - JNO_rel8( end ); // 21.840 - load_imm32( R_EDX, 1 ); // 51.841 - store_spreg( R_EDX, R_MACH ); // 61.842 - JS_rel8( positive ); // 21.843 - load_imm32( R_EAX, 0x80000000 );// 51.844 - store_spreg( R_EAX, R_MACL ); // 61.845 - JMP_rel8(end2); // 21.846 + ADDL_r32_rbpdisp( REG_EAX, R_MACL ); // 61.847 + JNO_label( end ); // 21.848 + load_imm32( REG_EDX, 1 ); // 51.849 + store_spreg( REG_EDX, R_MACH ); // 61.850 + JS_label( positive ); // 21.851 + load_imm32( REG_EAX, 0x80000000 );// 51.852 + store_spreg( REG_EAX, R_MACL ); // 61.853 + JMP_label(end2); // 21.855 JMP_TARGET(positive);1.856 - load_imm32( R_EAX, 0x7FFFFFFF );// 51.857 - store_spreg( R_EAX, R_MACL ); // 61.858 - JMP_rel8(end3); // 21.859 + load_imm32( REG_EAX, 0x7FFFFFFF );// 51.860 + store_spreg( REG_EAX, R_MACL ); // 61.861 + JMP_label(end3); // 21.863 JMP_TARGET(nosat);1.864 - ADD_r32_sh4r( R_EAX, R_MACL ); // 61.865 - ADC_r32_sh4r( R_EDX, R_MACH ); // 61.866 + ADDL_r32_rbpdisp( REG_EAX, R_MACL ); // 61.867 + ADCL_r32_rbpdisp( REG_EDX, R_MACH ); // 61.868 JMP_TARGET(end);1.869 JMP_TARGET(end2);1.870 JMP_TARGET(end3);1.871 @@ -738,556 +741,556 @@1.872 :}1.873 MOVT Rn {:1.874 COUNT_INST(I_MOVT);1.875 - load_spreg( R_EAX, R_T );1.876 - store_reg( R_EAX, Rn );1.877 + load_spreg( REG_EAX, R_T );1.878 + store_reg( REG_EAX, Rn );1.879 :}1.880 MUL.L Rm, Rn {:1.881 COUNT_INST(I_MULL);1.882 - load_reg( R_EAX, Rm );1.883 - load_reg( R_ECX, Rn );1.884 - MUL_r32( R_ECX );1.885 - store_spreg( R_EAX, R_MACL );1.886 + load_reg( REG_EAX, Rm );1.887 + load_reg( REG_ECX, Rn );1.888 + MULL_r32( REG_ECX );1.889 + store_spreg( REG_EAX, R_MACL );1.890 sh4_x86.tstate = TSTATE_NONE;1.891 :}1.892 MULS.W Rm, Rn {:1.893 COUNT_INST(I_MULSW);1.894 - load_reg16s( R_EAX, Rm );1.895 - load_reg16s( R_ECX, Rn );1.896 - MUL_r32( R_ECX );1.897 - store_spreg( R_EAX, R_MACL );1.898 + load_reg16s( REG_EAX, Rm );1.899 + load_reg16s( REG_ECX, Rn );1.900 + MULL_r32( REG_ECX );1.901 + store_spreg( REG_EAX, R_MACL );1.902 sh4_x86.tstate = TSTATE_NONE;1.903 :}1.904 MULU.W Rm, Rn {:1.905 COUNT_INST(I_MULUW);1.906 - load_reg16u( R_EAX, Rm );1.907 - load_reg16u( R_ECX, Rn );1.908 - MUL_r32( R_ECX );1.909 - store_spreg( R_EAX, R_MACL );1.910 + load_reg16u( REG_EAX, Rm );1.911 + load_reg16u( REG_ECX, Rn );1.912 + MULL_r32( REG_ECX );1.913 + store_spreg( REG_EAX, R_MACL );1.914 sh4_x86.tstate = TSTATE_NONE;1.915 :}1.916 NEG Rm, Rn {:1.917 COUNT_INST(I_NEG);1.918 - load_reg( R_EAX, Rm );1.919 - NEG_r32( R_EAX );1.920 - store_reg( R_EAX, Rn );1.921 + load_reg( REG_EAX, Rm );1.922 + NEGL_r32( REG_EAX );1.923 + store_reg( REG_EAX, Rn );1.924 sh4_x86.tstate = TSTATE_NONE;1.925 :}1.926 NEGC Rm, Rn {:1.927 COUNT_INST(I_NEGC);1.928 - load_reg( R_EAX, Rm );1.929 - XOR_r32_r32( R_ECX, R_ECX );1.930 + load_reg( REG_EAX, Rm );1.931 + XORL_r32_r32( REG_ECX, REG_ECX );1.932 LDC_t();1.933 - SBB_r32_r32( R_EAX, R_ECX );1.934 - store_reg( R_ECX, Rn );1.935 + SBBL_r32_r32( REG_EAX, REG_ECX );1.936 + store_reg( REG_ECX, Rn );1.937 SETC_t();1.938 sh4_x86.tstate = TSTATE_C;1.939 :}1.940 NOT Rm, Rn {:1.941 COUNT_INST(I_NOT);1.942 - load_reg( R_EAX, Rm );1.943 - NOT_r32( R_EAX );1.944 - store_reg( R_EAX, Rn );1.945 + load_reg( REG_EAX, Rm );1.946 + NOTL_r32( REG_EAX );1.947 + store_reg( REG_EAX, Rn );1.948 sh4_x86.tstate = TSTATE_NONE;1.949 :}1.950 OR Rm, Rn {:1.951 COUNT_INST(I_OR);1.952 - load_reg( R_EAX, Rm );1.953 - load_reg( R_ECX, Rn );1.954 - OR_r32_r32( R_EAX, R_ECX );1.955 - store_reg( R_ECX, Rn );1.956 + load_reg( REG_EAX, Rm );1.957 + load_reg( REG_ECX, Rn );1.958 + ORL_r32_r32( REG_EAX, REG_ECX );1.959 + store_reg( REG_ECX, Rn );1.960 sh4_x86.tstate = TSTATE_NONE;1.961 :}1.962 OR #imm, R0 {:1.963 COUNT_INST(I_ORI);1.964 - load_reg( R_EAX, 0 );1.965 - OR_imm32_r32(imm, R_EAX);1.966 - store_reg( R_EAX, 0 );1.967 + load_reg( REG_EAX, 0 );1.968 + ORL_imms_r32(imm, REG_EAX);1.969 + store_reg( REG_EAX, 0 );1.970 sh4_x86.tstate = TSTATE_NONE;1.971 :}1.972 OR.B #imm, @(R0, GBR) {:1.973 COUNT_INST(I_ORB);1.974 - load_reg( R_EAX, 0 );1.975 - ADD_sh4r_r32( R_GBR, R_EAX );1.976 - MOV_r32_esp8( R_EAX, 0 );1.977 - MEM_READ_BYTE_FOR_WRITE( R_EAX, R_EDX );1.978 - MOV_esp8_r32( 0, R_EAX );1.979 - OR_imm32_r32(imm, R_EDX );1.980 - MEM_WRITE_BYTE( R_EAX, R_EDX );1.981 + load_reg( REG_EAX, 0 );1.982 + ADDL_rbpdisp_r32( R_GBR, REG_EAX );1.983 + MOVL_r32_rspdisp( REG_EAX, 0 );1.984 + MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );1.985 + MOVL_rspdisp_r32( 0, REG_EAX );1.986 + ORL_imms_r32(imm, REG_EDX );1.987 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );1.988 sh4_x86.tstate = TSTATE_NONE;1.989 :}1.990 ROTCL Rn {:1.991 COUNT_INST(I_ROTCL);1.992 - load_reg( R_EAX, Rn );1.993 + load_reg( REG_EAX, Rn );1.994 if( sh4_x86.tstate != TSTATE_C ) {1.995 LDC_t();1.996 }1.997 - RCL1_r32( R_EAX );1.998 - store_reg( R_EAX, Rn );1.999 + RCLL_imm_r32( 1, REG_EAX );1.1000 + store_reg( REG_EAX, Rn );1.1001 SETC_t();1.1002 sh4_x86.tstate = TSTATE_C;1.1003 :}1.1004 ROTCR Rn {:1.1005 COUNT_INST(I_ROTCR);1.1006 - load_reg( R_EAX, Rn );1.1007 + load_reg( REG_EAX, Rn );1.1008 if( sh4_x86.tstate != TSTATE_C ) {1.1009 LDC_t();1.1010 }1.1011 - RCR1_r32( R_EAX );1.1012 - store_reg( R_EAX, Rn );1.1013 + RCRL_imm_r32( 1, REG_EAX );1.1014 + store_reg( REG_EAX, Rn );1.1015 SETC_t();1.1016 sh4_x86.tstate = TSTATE_C;1.1017 :}1.1018 ROTL Rn {:1.1019 COUNT_INST(I_ROTL);1.1020 - load_reg( R_EAX, Rn );1.1021 - ROL1_r32( R_EAX );1.1022 - store_reg( R_EAX, Rn );1.1023 + load_reg( REG_EAX, Rn );1.1024 + ROLL_imm_r32( 1, REG_EAX );1.1025 + store_reg( REG_EAX, Rn );1.1026 SETC_t();1.1027 sh4_x86.tstate = TSTATE_C;1.1028 :}1.1029 ROTR Rn {:1.1030 COUNT_INST(I_ROTR);1.1031 - load_reg( R_EAX, Rn );1.1032 - ROR1_r32( R_EAX );1.1033 - store_reg( R_EAX, Rn );1.1034 + load_reg( REG_EAX, Rn );1.1035 + RORL_imm_r32( 1, REG_EAX );1.1036 + store_reg( REG_EAX, Rn );1.1037 SETC_t();1.1038 sh4_x86.tstate = TSTATE_C;1.1039 :}1.1040 SHAD Rm, Rn {:1.1041 COUNT_INST(I_SHAD);1.1042 /* Annoyingly enough, not directly convertible */1.1043 - load_reg( R_EAX, Rn );1.1044 - load_reg( R_ECX, Rm );1.1045 - CMP_imm32_r32( 0, R_ECX );1.1046 - JGE_rel8(doshl);1.1047 + load_reg( REG_EAX, Rn );1.1048 + load_reg( REG_ECX, Rm );1.1049 + CMPL_imms_r32( 0, REG_ECX );1.1050 + JGE_label(doshl);1.1052 - NEG_r32( R_ECX ); // 21.1053 - AND_imm8_r8( 0x1F, R_CL ); // 31.1054 - JE_rel8(emptysar); // 21.1055 - SAR_r32_CL( R_EAX ); // 21.1056 - JMP_rel8(end); // 21.1057 + NEGL_r32( REG_ECX ); // 21.1058 + ANDB_imms_r8( 0x1F, REG_CL ); // 31.1059 + JE_label(emptysar); // 21.1060 + SARL_cl_r32( REG_EAX ); // 21.1061 + JMP_label(end); // 21.1063 JMP_TARGET(emptysar);1.1064 - SAR_imm8_r32(31, R_EAX ); // 31.1065 - JMP_rel8(end2);1.1066 + SARL_imm_r32(31, REG_EAX ); // 31.1067 + JMP_label(end2);1.1069 JMP_TARGET(doshl);1.1070 - AND_imm8_r8( 0x1F, R_CL ); // 31.1071 - SHL_r32_CL( R_EAX ); // 21.1072 + ANDB_imms_r8( 0x1F, REG_CL ); // 31.1073 + SHLL_cl_r32( REG_EAX ); // 21.1074 JMP_TARGET(end);1.1075 JMP_TARGET(end2);1.1076 - store_reg( R_EAX, Rn );1.1077 + store_reg( REG_EAX, Rn );1.1078 sh4_x86.tstate = TSTATE_NONE;1.1079 :}1.1080 SHLD Rm, Rn {:1.1081 COUNT_INST(I_SHLD);1.1082 - load_reg( R_EAX, Rn );1.1083 - load_reg( R_ECX, Rm );1.1084 - CMP_imm32_r32( 0, R_ECX );1.1085 - JGE_rel8(doshl);1.1086 + load_reg( REG_EAX, Rn );1.1087 + load_reg( REG_ECX, Rm );1.1088 + CMPL_imms_r32( 0, REG_ECX );1.1089 + JGE_label(doshl);1.1091 - NEG_r32( R_ECX ); // 21.1092 - AND_imm8_r8( 0x1F, R_CL ); // 31.1093 - JE_rel8(emptyshr );1.1094 - SHR_r32_CL( R_EAX ); // 21.1095 - JMP_rel8(end); // 21.1096 + NEGL_r32( REG_ECX ); // 21.1097 + ANDB_imms_r8( 0x1F, REG_CL ); // 31.1098 + JE_label(emptyshr );1.1099 + SHRL_cl_r32( REG_EAX ); // 21.1100 + JMP_label(end); // 21.1102 JMP_TARGET(emptyshr);1.1103 - XOR_r32_r32( R_EAX, R_EAX );1.1104 - JMP_rel8(end2);1.1105 + XORL_r32_r32( REG_EAX, REG_EAX );1.1106 + JMP_label(end2);1.1108 JMP_TARGET(doshl);1.1109 - AND_imm8_r8( 0x1F, R_CL ); // 31.1110 - SHL_r32_CL( R_EAX ); // 21.1111 + ANDB_imms_r8( 0x1F, REG_CL ); // 31.1112 + SHLL_cl_r32( REG_EAX ); // 21.1113 JMP_TARGET(end);1.1114 JMP_TARGET(end2);1.1115 - store_reg( R_EAX, Rn );1.1116 + store_reg( REG_EAX, Rn );1.1117 sh4_x86.tstate = TSTATE_NONE;1.1118 :}1.1119 SHAL Rn {:1.1120 COUNT_INST(I_SHAL);1.1121 - load_reg( R_EAX, Rn );1.1122 - SHL1_r32( R_EAX );1.1123 + load_reg( REG_EAX, Rn );1.1124 + SHLL_imm_r32( 1, REG_EAX );1.1125 SETC_t();1.1126 - store_reg( R_EAX, Rn );1.1127 + store_reg( REG_EAX, Rn );1.1128 sh4_x86.tstate = TSTATE_C;1.1129 :}1.1130 SHAR Rn {:1.1131 COUNT_INST(I_SHAR);1.1132 - load_reg( R_EAX, Rn );1.1133 - SAR1_r32( R_EAX );1.1134 + load_reg( REG_EAX, Rn );1.1135 + SARL_imm_r32( 1, REG_EAX );1.1136 SETC_t();1.1137 - store_reg( R_EAX, Rn );1.1138 + store_reg( REG_EAX, Rn );1.1139 sh4_x86.tstate = TSTATE_C;1.1140 :}1.1141 SHLL Rn {:1.1142 COUNT_INST(I_SHLL);1.1143 - load_reg( R_EAX, Rn );1.1144 - SHL1_r32( R_EAX );1.1145 + load_reg( REG_EAX, Rn );1.1146 + SHLL_imm_r32( 1, REG_EAX );1.1147 SETC_t();1.1148 - store_reg( R_EAX, Rn );1.1149 + store_reg( REG_EAX, Rn );1.1150 sh4_x86.tstate = TSTATE_C;1.1151 :}1.1152 SHLL2 Rn {:1.1153 COUNT_INST(I_SHLL);1.1154 - load_reg( R_EAX, Rn );1.1155 - SHL_imm8_r32( 2, R_EAX );1.1156 - store_reg( R_EAX, Rn );1.1157 + load_reg( REG_EAX, Rn );1.1158 + SHLL_imm_r32( 2, REG_EAX );1.1159 + store_reg( REG_EAX, Rn );1.1160 sh4_x86.tstate = TSTATE_NONE;1.1161 :}1.1162 SHLL8 Rn {:1.1163 COUNT_INST(I_SHLL);1.1164 - load_reg( R_EAX, Rn );1.1165 - SHL_imm8_r32( 8, R_EAX );1.1166 - store_reg( R_EAX, Rn );1.1167 + load_reg( REG_EAX, Rn );1.1168 + SHLL_imm_r32( 8, REG_EAX );1.1169 + store_reg( REG_EAX, Rn );1.1170 sh4_x86.tstate = TSTATE_NONE;1.1171 :}1.1172 SHLL16 Rn {:1.1173 COUNT_INST(I_SHLL);1.1174 - load_reg( R_EAX, Rn );1.1175 - SHL_imm8_r32( 16, R_EAX );1.1176 - store_reg( R_EAX, Rn );1.1177 + load_reg( REG_EAX, Rn );1.1178 + SHLL_imm_r32( 16, REG_EAX );1.1179 + store_reg( REG_EAX, Rn );1.1180 sh4_x86.tstate = TSTATE_NONE;1.1181 :}1.1182 SHLR Rn {:1.1183 COUNT_INST(I_SHLR);1.1184 - load_reg( R_EAX, Rn );1.1185 - SHR1_r32( R_EAX );1.1186 + load_reg( REG_EAX, Rn );1.1187 + SHRL_imm_r32( 1, REG_EAX );1.1188 SETC_t();1.1189 - store_reg( R_EAX, Rn );1.1190 + store_reg( REG_EAX, Rn );1.1191 sh4_x86.tstate = TSTATE_C;1.1192 :}1.1193 SHLR2 Rn {:1.1194 COUNT_INST(I_SHLR);1.1195 - load_reg( R_EAX, Rn );1.1196 - SHR_imm8_r32( 2, R_EAX );1.1197 - store_reg( R_EAX, Rn );1.1198 + load_reg( REG_EAX, Rn );1.1199 + SHRL_imm_r32( 2, REG_EAX );1.1200 + store_reg( REG_EAX, Rn );1.1201 sh4_x86.tstate = TSTATE_NONE;1.1202 :}1.1203 SHLR8 Rn {:1.1204 COUNT_INST(I_SHLR);1.1205 - load_reg( R_EAX, Rn );1.1206 - SHR_imm8_r32( 8, R_EAX );1.1207 - store_reg( R_EAX, Rn );1.1208 + load_reg( REG_EAX, Rn );1.1209 + SHRL_imm_r32( 8, REG_EAX );1.1210 + store_reg( REG_EAX, Rn );1.1211 sh4_x86.tstate = TSTATE_NONE;1.1212 :}1.1213 SHLR16 Rn {:1.1214 COUNT_INST(I_SHLR);1.1215 - load_reg( R_EAX, Rn );1.1216 - SHR_imm8_r32( 16, R_EAX );1.1217 - store_reg( R_EAX, Rn );1.1218 + load_reg( REG_EAX, Rn );1.1219 + SHRL_imm_r32( 16, REG_EAX );1.1220 + store_reg( REG_EAX, Rn );1.1221 sh4_x86.tstate = TSTATE_NONE;1.1222 :}1.1223 SUB Rm, Rn {:1.1224 COUNT_INST(I_SUB);1.1225 - load_reg( R_EAX, Rm );1.1226 - load_reg( R_ECX, Rn );1.1227 - SUB_r32_r32( R_EAX, R_ECX );1.1228 - store_reg( R_ECX, Rn );1.1229 + load_reg( REG_EAX, Rm );1.1230 + load_reg( REG_ECX, Rn );1.1231 + SUBL_r32_r32( REG_EAX, REG_ECX );1.1232 + store_reg( REG_ECX, Rn );1.1233 sh4_x86.tstate = TSTATE_NONE;1.1234 :}1.1235 SUBC Rm, Rn {:1.1236 COUNT_INST(I_SUBC);1.1237 - load_reg( R_EAX, Rm );1.1238 - load_reg( R_ECX, Rn );1.1239 + load_reg( REG_EAX, Rm );1.1240 + load_reg( REG_ECX, Rn );1.1241 if( sh4_x86.tstate != TSTATE_C ) {1.1242 LDC_t();1.1243 }1.1244 - SBB_r32_r32( R_EAX, R_ECX );1.1245 - store_reg( R_ECX, Rn );1.1246 + SBBL_r32_r32( REG_EAX, REG_ECX );1.1247 + store_reg( REG_ECX, Rn );1.1248 SETC_t();1.1249 sh4_x86.tstate = TSTATE_C;1.1250 :}1.1251 SUBV Rm, Rn {:1.1252 COUNT_INST(I_SUBV);1.1253 - load_reg( R_EAX, Rm );1.1254 - load_reg( R_ECX, Rn );1.1255 - SUB_r32_r32( R_EAX, R_ECX );1.1256 - store_reg( R_ECX, Rn );1.1257 + load_reg( REG_EAX, Rm );1.1258 + load_reg( REG_ECX, Rn );1.1259 + SUBL_r32_r32( REG_EAX, REG_ECX );1.1260 + store_reg( REG_ECX, Rn );1.1261 SETO_t();1.1262 sh4_x86.tstate = TSTATE_O;1.1263 :}1.1264 SWAP.B Rm, Rn {:1.1265 COUNT_INST(I_SWAPB);1.1266 - load_reg( R_EAX, Rm );1.1267 - XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS1.1268 - store_reg( R_EAX, Rn );1.1269 + load_reg( REG_EAX, Rm );1.1270 + XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS1.1271 + store_reg( REG_EAX, Rn );1.1272 :}1.1273 SWAP.W Rm, Rn {:1.1274 COUNT_INST(I_SWAPB);1.1275 - load_reg( R_EAX, Rm );1.1276 - MOV_r32_r32( R_EAX, R_ECX );1.1277 - SHL_imm8_r32( 16, R_ECX );1.1278 - SHR_imm8_r32( 16, R_EAX );1.1279 - OR_r32_r32( R_EAX, R_ECX );1.1280 - store_reg( R_ECX, Rn );1.1281 + load_reg( REG_EAX, Rm );1.1282 + MOVL_r32_r32( REG_EAX, REG_ECX );1.1283 + SHLL_imm_r32( 16, REG_ECX );1.1284 + SHRL_imm_r32( 16, REG_EAX );1.1285 + ORL_r32_r32( REG_EAX, REG_ECX );1.1286 + store_reg( REG_ECX, Rn );1.1287 sh4_x86.tstate = TSTATE_NONE;1.1288 :}1.1289 TAS.B @Rn {:1.1290 COUNT_INST(I_TASB);1.1291 - load_reg( R_EAX, Rn );1.1292 - MOV_r32_esp8( R_EAX, 0 );1.1293 - MEM_READ_BYTE_FOR_WRITE( R_EAX, R_EDX );1.1294 - TEST_r8_r8( R_DL, R_DL );1.1295 + load_reg( REG_EAX, Rn );1.1296 + MOVL_r32_rspdisp( REG_EAX, 0 );1.1297 + MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );1.1298 + TESTB_r8_r8( REG_DL, REG_DL );1.1299 SETE_t();1.1300 - OR_imm8_r8( 0x80, R_DL );1.1301 - MOV_esp8_r32( 0, R_EAX );1.1302 - MEM_WRITE_BYTE( R_EAX, R_EDX );1.1303 + ORB_imms_r8( 0x80, REG_DL );1.1304 + MOVL_rspdisp_r32( 0, REG_EAX );1.1305 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );1.1306 sh4_x86.tstate = TSTATE_NONE;1.1307 :}1.1308 TST Rm, Rn {:1.1309 COUNT_INST(I_TST);1.1310 - load_reg( R_EAX, Rm );1.1311 - load_reg( R_ECX, Rn );1.1312 - TEST_r32_r32( R_EAX, R_ECX );1.1313 + load_reg( REG_EAX, Rm );1.1314 + load_reg( REG_ECX, Rn );1.1315 + TESTL_r32_r32( REG_EAX, REG_ECX );1.1316 SETE_t();1.1317 sh4_x86.tstate = TSTATE_E;1.1318 :}1.1319 TST #imm, R0 {:1.1320 COUNT_INST(I_TSTI);1.1321 - load_reg( R_EAX, 0 );1.1322 - TEST_imm32_r32( imm, R_EAX );1.1323 + load_reg( REG_EAX, 0 );1.1324 + TESTL_imms_r32( imm, REG_EAX );1.1325 SETE_t();1.1326 sh4_x86.tstate = TSTATE_E;1.1327 :}1.1328 TST.B #imm, @(R0, GBR) {:1.1329 COUNT_INST(I_TSTB);1.1330 - load_reg( R_EAX, 0);1.1331 - ADD_sh4r_r32( R_GBR, R_EAX );1.1332 - MEM_READ_BYTE( R_EAX, R_EAX );1.1333 - TEST_imm8_r8( imm, R_AL );1.1334 + load_reg( REG_EAX, 0);1.1335 + ADDL_rbpdisp_r32( R_GBR, REG_EAX );1.1336 + MEM_READ_BYTE( REG_EAX, REG_EAX );1.1337 + TESTB_imms_r8( imm, REG_AL );1.1338 SETE_t();1.1339 sh4_x86.tstate = TSTATE_E;1.1340 :}1.1341 XOR Rm, Rn {:1.1342 COUNT_INST(I_XOR);1.1343 - load_reg( R_EAX, Rm );1.1344 - load_reg( R_ECX, Rn );1.1345 - XOR_r32_r32( R_EAX, R_ECX );1.1346 - store_reg( R_ECX, Rn );1.1347 + load_reg( REG_EAX, Rm );1.1348 + load_reg( REG_ECX, Rn );1.1349 + XORL_r32_r32( REG_EAX, REG_ECX );1.1350 + store_reg( REG_ECX, Rn );1.1351 sh4_x86.tstate = TSTATE_NONE;1.1352 :}1.1353 XOR #imm, R0 {:1.1354 COUNT_INST(I_XORI);1.1355 - load_reg( R_EAX, 0 );1.1356 - XOR_imm32_r32( imm, R_EAX );1.1357 - store_reg( R_EAX, 0 );1.1358 + load_reg( REG_EAX, 0 );1.1359 + XORL_imms_r32( imm, REG_EAX );1.1360 + store_reg( REG_EAX, 0 );1.1361 sh4_x86.tstate = TSTATE_NONE;1.1362 :}1.1363 XOR.B #imm, @(R0, GBR) {:1.1364 COUNT_INST(I_XORB);1.1365 - load_reg( R_EAX, 0 );1.1366 - ADD_sh4r_r32( R_GBR, R_EAX );1.1367 - MOV_r32_esp8( R_EAX, 0 );1.1368 - MEM_READ_BYTE_FOR_WRITE(R_EAX, R_EDX);1.1369 - MOV_esp8_r32( 0, R_EAX );1.1370 - XOR_imm32_r32( imm, R_EDX );1.1371 - MEM_WRITE_BYTE( R_EAX, R_EDX );1.1372 + load_reg( REG_EAX, 0 );1.1373 + ADDL_rbpdisp_r32( R_GBR, REG_EAX );1.1374 + MOVL_r32_rspdisp( REG_EAX, 0 );1.1375 + MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);1.1376 + MOVL_rspdisp_r32( 0, REG_EAX );1.1377 + XORL_imms_r32( imm, REG_EDX );1.1378 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );1.1379 sh4_x86.tstate = TSTATE_NONE;1.1380 :}1.1381 XTRCT Rm, Rn {:1.1382 COUNT_INST(I_XTRCT);1.1383 - load_reg( R_EAX, Rm );1.1384 - load_reg( R_ECX, Rn );1.1385 - SHL_imm8_r32( 16, R_EAX );1.1386 - SHR_imm8_r32( 16, R_ECX );1.1387 - OR_r32_r32( R_EAX, R_ECX );1.1388 - store_reg( R_ECX, Rn );1.1389 + load_reg( REG_EAX, Rm );1.1390 + load_reg( REG_ECX, Rn );1.1391 + SHLL_imm_r32( 16, REG_EAX );1.1392 + SHRL_imm_r32( 16, REG_ECX );1.1393 + ORL_r32_r32( REG_EAX, REG_ECX );1.1394 + store_reg( REG_ECX, Rn );1.1395 sh4_x86.tstate = TSTATE_NONE;1.1396 :}1.1398 /* Data move instructions */1.1399 MOV Rm, Rn {:1.1400 COUNT_INST(I_MOV);1.1401 - load_reg( R_EAX, Rm );1.1402 - store_reg( R_EAX, Rn );1.1403 + load_reg( REG_EAX, Rm );1.1404 + store_reg( REG_EAX, Rn );1.1405 :}1.1406 MOV #imm, Rn {:1.1407 COUNT_INST(I_MOVI);1.1408 - load_imm32( R_EAX, imm );1.1409 - store_reg( R_EAX, Rn );1.1410 + load_imm32( REG_EAX, imm );1.1411 + store_reg( REG_EAX, Rn );1.1412 :}1.1413 MOV.B Rm, @Rn {:1.1414 COUNT_INST(I_MOVB);1.1415 - load_reg( R_EAX, Rn );1.1416 - load_reg( R_EDX, Rm );1.1417 - MEM_WRITE_BYTE( R_EAX, R_EDX );1.1418 + load_reg( REG_EAX, Rn );1.1419 + load_reg( REG_EDX, Rm );1.1420 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );1.1421 sh4_x86.tstate = TSTATE_NONE;1.1422 :}1.1423 MOV.B Rm, @-Rn {:1.1424 COUNT_INST(I_MOVB);1.1425 - load_reg( R_EAX, Rn );1.1426 - LEA_r32disp8_r32( R_EAX, -1, R_EAX );1.1427 - load_reg( R_EDX, Rm );1.1428 - MEM_WRITE_BYTE( R_EAX, R_EDX );1.1429 - ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );1.1430 + load_reg( REG_EAX, Rn );1.1431 + LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );1.1432 + load_reg( REG_EDX, Rm );1.1433 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );1.1434 + ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );1.1435 sh4_x86.tstate = TSTATE_NONE;1.1436 :}1.1437 MOV.B Rm, @(R0, Rn) {:1.1438 COUNT_INST(I_MOVB);1.1439 - load_reg( R_EAX, 0 );1.1440 - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );1.1441 - load_reg( R_EDX, Rm );1.1442 - MEM_WRITE_BYTE( R_EAX, R_EDX );1.1443 + load_reg( REG_EAX, 0 );1.1444 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );1.1445 + load_reg( REG_EDX, Rm );1.1446 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );1.1447 sh4_x86.tstate = TSTATE_NONE;1.1448 :}1.1449 MOV.B R0, @(disp, GBR) {:1.1450 COUNT_INST(I_MOVB);1.1451 - load_spreg( R_EAX, R_GBR );1.1452 - ADD_imm32_r32( disp, R_EAX );1.1453 - load_reg( R_EDX, 0 );1.1454 - MEM_WRITE_BYTE( R_EAX, R_EDX );1.1455 + load_spreg( REG_EAX, R_GBR );1.1456 + ADDL_imms_r32( disp, REG_EAX );1.1457 + load_reg( REG_EDX, 0 );1.1458 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );1.1459 sh4_x86.tstate = TSTATE_NONE;1.1460 :}1.1461 MOV.B R0, @(disp, Rn) {:1.1462 COUNT_INST(I_MOVB);1.1463 - load_reg( R_EAX, Rn );1.1464 - ADD_imm32_r32( disp, R_EAX );1.1465 - load_reg( R_EDX, 0 );1.1466 - MEM_WRITE_BYTE( R_EAX, R_EDX );1.1467 + load_reg( REG_EAX, Rn );1.1468 + ADDL_imms_r32( disp, REG_EAX );1.1469 + load_reg( REG_EDX, 0 );1.1470 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );1.1471 sh4_x86.tstate = TSTATE_NONE;1.1472 :}1.1473 MOV.B @Rm, Rn {:1.1474 COUNT_INST(I_MOVB);1.1475 - load_reg( R_EAX, Rm );1.1476 - MEM_READ_BYTE( R_EAX, R_EAX );1.1477 - store_reg( R_EAX, Rn );1.1478 + load_reg( REG_EAX, Rm );1.1479 + MEM_READ_BYTE( REG_EAX, REG_EAX );1.1480 + store_reg( REG_EAX, Rn );1.1481 sh4_x86.tstate = TSTATE_NONE;1.1482 :}1.1483 MOV.B @Rm+, Rn {:1.1484 COUNT_INST(I_MOVB);1.1485 - load_reg( R_EAX, Rm );1.1486 - MEM_READ_BYTE( R_EAX, R_EAX );1.1487 + load_reg( REG_EAX, Rm );1.1488 + MEM_READ_BYTE( REG_EAX, REG_EAX );1.1489 if( Rm != Rn ) {1.1490 - ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );1.1491 + ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );1.1492 }1.1493 - store_reg( R_EAX, Rn );1.1494 + store_reg( REG_EAX, Rn );1.1495 sh4_x86.tstate = TSTATE_NONE;1.1496 :}1.1497 MOV.B @(R0, Rm), Rn {:1.1498 COUNT_INST(I_MOVB);1.1499 - load_reg( R_EAX, 0 );1.1500 - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );1.1501 - MEM_READ_BYTE( R_EAX, R_EAX );1.1502 - store_reg( R_EAX, Rn );1.1503 + load_reg( REG_EAX, 0 );1.1504 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );1.1505 + MEM_READ_BYTE( REG_EAX, REG_EAX );1.1506 + store_reg( REG_EAX, Rn );1.1507 sh4_x86.tstate = TSTATE_NONE;1.1508 :}1.1509 MOV.B @(disp, GBR), R0 {:1.1510 COUNT_INST(I_MOVB);1.1511 - load_spreg( R_EAX, R_GBR );1.1512 - ADD_imm32_r32( disp, R_EAX );1.1513 - MEM_READ_BYTE( R_EAX, R_EAX );1.1514 - store_reg( R_EAX, 0 );1.1515 + load_spreg( REG_EAX, R_GBR );1.1516 + ADDL_imms_r32( disp, REG_EAX );1.1517 + MEM_READ_BYTE( REG_EAX, REG_EAX );1.1518 + store_reg( REG_EAX, 0 );1.1519 sh4_x86.tstate = TSTATE_NONE;1.1520 :}1.1521 MOV.B @(disp, Rm), R0 {:1.1522 COUNT_INST(I_MOVB);1.1523 - load_reg( R_EAX, Rm );1.1524 - ADD_imm32_r32( disp, R_EAX );1.1525 - MEM_READ_BYTE( R_EAX, R_EAX );1.1526 - store_reg( R_EAX, 0 );1.1527 + load_reg( REG_EAX, Rm );1.1528 + ADDL_imms_r32( disp, REG_EAX );1.1529 + MEM_READ_BYTE( REG_EAX, REG_EAX );1.1530 + store_reg( REG_EAX, 0 );1.1531 sh4_x86.tstate = TSTATE_NONE;1.1532 :}1.1533 MOV.L Rm, @Rn {:1.1534 COUNT_INST(I_MOVL);1.1535 - load_reg( R_EAX, Rn );1.1536 - check_walign32(R_EAX);1.1537 - MOV_r32_r32( R_EAX, R_ECX );1.1538 - AND_imm32_r32( 0xFC000000, R_ECX );1.1539 - CMP_imm32_r32( 0xE0000000, R_ECX );1.1540 - JNE_rel8( notsq );1.1541 - AND_imm8s_r32( 0x3C, R_EAX );1.1542 - load_reg( R_EDX, Rm );1.1543 - MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );1.1544 - JMP_rel8(end);1.1545 + load_reg( REG_EAX, Rn );1.1546 + check_walign32(REG_EAX);1.1547 + MOVL_r32_r32( REG_EAX, REG_ECX );1.1548 + ANDL_imms_r32( 0xFC000000, REG_ECX );1.1549 + CMPL_imms_r32( 0xE0000000, REG_ECX );1.1550 + JNE_label( notsq );1.1551 + ANDL_imms_r32( 0x3C, REG_EAX );1.1552 + load_reg( REG_EDX, Rm );1.1553 + MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );1.1554 + JMP_label(end);1.1555 JMP_TARGET(notsq);1.1556 - load_reg( R_EDX, Rm );1.1557 - MEM_WRITE_LONG( R_EAX, R_EDX );1.1558 + load_reg( REG_EDX, Rm );1.1559 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.1560 JMP_TARGET(end);1.1561 sh4_x86.tstate = TSTATE_NONE;1.1562 :}1.1563 MOV.L Rm, @-Rn {:1.1564 COUNT_INST(I_MOVL);1.1565 - load_reg( R_EAX, Rn );1.1566 - ADD_imm8s_r32( -4, R_EAX );1.1567 - check_walign32( R_EAX );1.1568 - load_reg( R_EDX, Rm );1.1569 - MEM_WRITE_LONG( R_EAX, R_EDX );1.1570 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.1571 + load_reg( REG_EAX, Rn );1.1572 + ADDL_imms_r32( -4, REG_EAX );1.1573 + check_walign32( REG_EAX );1.1574 + load_reg( REG_EDX, Rm );1.1575 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.1576 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.1577 sh4_x86.tstate = TSTATE_NONE;1.1578 :}1.1579 MOV.L Rm, @(R0, Rn) {:1.1580 COUNT_INST(I_MOVL);1.1581 - load_reg( R_EAX, 0 );1.1582 - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );1.1583 - check_walign32( R_EAX );1.1584 - load_reg( R_EDX, Rm );1.1585 - MEM_WRITE_LONG( R_EAX, R_EDX );1.1586 + load_reg( REG_EAX, 0 );1.1587 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );1.1588 + check_walign32( REG_EAX );1.1589 + load_reg( REG_EDX, Rm );1.1590 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.1591 sh4_x86.tstate = TSTATE_NONE;1.1592 :}1.1593 MOV.L R0, @(disp, GBR) {:1.1594 COUNT_INST(I_MOVL);1.1595 - load_spreg( R_EAX, R_GBR );1.1596 - ADD_imm32_r32( disp, R_EAX );1.1597 - check_walign32( R_EAX );1.1598 - load_reg( R_EDX, 0 );1.1599 - MEM_WRITE_LONG( R_EAX, R_EDX );1.1600 + load_spreg( REG_EAX, R_GBR );1.1601 + ADDL_imms_r32( disp, REG_EAX );1.1602 + check_walign32( REG_EAX );1.1603 + load_reg( REG_EDX, 0 );1.1604 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.1605 sh4_x86.tstate = TSTATE_NONE;1.1606 :}1.1607 MOV.L Rm, @(disp, Rn) {:1.1608 COUNT_INST(I_MOVL);1.1609 - load_reg( R_EAX, Rn );1.1610 - ADD_imm32_r32( disp, R_EAX );1.1611 - check_walign32( R_EAX );1.1612 - MOV_r32_r32( R_EAX, R_ECX );1.1613 - AND_imm32_r32( 0xFC000000, R_ECX );1.1614 - CMP_imm32_r32( 0xE0000000, R_ECX );1.1615 - JNE_rel8( notsq );1.1616 - AND_imm8s_r32( 0x3C, R_EAX );1.1617 - load_reg( R_EDX, Rm );1.1618 - MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );1.1619 - JMP_rel8(end);1.1620 + load_reg( REG_EAX, Rn );1.1621 + ADDL_imms_r32( disp, REG_EAX );1.1622 + check_walign32( REG_EAX );1.1623 + MOVL_r32_r32( REG_EAX, REG_ECX );1.1624 + ANDL_imms_r32( 0xFC000000, REG_ECX );1.1625 + CMPL_imms_r32( 0xE0000000, REG_ECX );1.1626 + JNE_label( notsq );1.1627 + ANDL_imms_r32( 0x3C, REG_EAX );1.1628 + load_reg( REG_EDX, Rm );1.1629 + MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );1.1630 + JMP_label(end);1.1631 JMP_TARGET(notsq);1.1632 - load_reg( R_EDX, Rm );1.1633 - MEM_WRITE_LONG( R_EAX, R_EDX );1.1634 + load_reg( REG_EDX, Rm );1.1635 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.1636 JMP_TARGET(end);1.1637 sh4_x86.tstate = TSTATE_NONE;1.1638 :}1.1639 MOV.L @Rm, Rn {:1.1640 COUNT_INST(I_MOVL);1.1641 - load_reg( R_EAX, Rm );1.1642 - check_ralign32( R_EAX );1.1643 - MEM_READ_LONG( R_EAX, R_EAX );1.1644 - store_reg( R_EAX, Rn );1.1645 + load_reg( REG_EAX, Rm );1.1646 + check_ralign32( REG_EAX );1.1647 + MEM_READ_LONG( REG_EAX, REG_EAX );1.1648 + store_reg( REG_EAX, Rn );1.1649 sh4_x86.tstate = TSTATE_NONE;1.1650 :}1.1651 MOV.L @Rm+, Rn {:1.1652 COUNT_INST(I_MOVL);1.1653 - load_reg( R_EAX, Rm );1.1654 - check_ralign32( R_EAX );1.1655 - MEM_READ_LONG( R_EAX, R_EAX );1.1656 + load_reg( REG_EAX, Rm );1.1657 + check_ralign32( REG_EAX );1.1658 + MEM_READ_LONG( REG_EAX, REG_EAX );1.1659 if( Rm != Rn ) {1.1660 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.1661 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.1662 }1.1663 - store_reg( R_EAX, Rn );1.1664 + store_reg( REG_EAX, Rn );1.1665 sh4_x86.tstate = TSTATE_NONE;1.1666 :}1.1667 MOV.L @(R0, Rm), Rn {:1.1668 COUNT_INST(I_MOVL);1.1669 - load_reg( R_EAX, 0 );1.1670 - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );1.1671 - check_ralign32( R_EAX );1.1672 - MEM_READ_LONG( R_EAX, R_EAX );1.1673 - store_reg( R_EAX, Rn );1.1674 + load_reg( REG_EAX, 0 );1.1675 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );1.1676 + check_ralign32( REG_EAX );1.1677 + MEM_READ_LONG( REG_EAX, REG_EAX );1.1678 + store_reg( REG_EAX, Rn );1.1679 sh4_x86.tstate = TSTATE_NONE;1.1680 :}1.1681 MOV.L @(disp, GBR), R0 {:1.1682 COUNT_INST(I_MOVL);1.1683 - load_spreg( R_EAX, R_GBR );1.1684 - ADD_imm32_r32( disp, R_EAX );1.1685 - check_ralign32( R_EAX );1.1686 - MEM_READ_LONG( R_EAX, R_EAX );1.1687 - store_reg( R_EAX, 0 );1.1688 + load_spreg( REG_EAX, R_GBR );1.1689 + ADDL_imms_r32( disp, REG_EAX );1.1690 + check_ralign32( REG_EAX );1.1691 + MEM_READ_LONG( REG_EAX, REG_EAX );1.1692 + store_reg( REG_EAX, 0 );1.1693 sh4_x86.tstate = TSTATE_NONE;1.1694 :}1.1695 MOV.L @(disp, PC), Rn {:1.1696 @@ -1307,108 +1310,108 @@1.1697 // behaviour to confirm) Unlikely to be anyone depending on this1.1698 // behaviour though.1.1699 sh4ptr_t ptr = GET_ICACHE_PTR(target);1.1700 - MOV_moff32_EAX( ptr );1.1701 + MOVL_moffptr_eax( ptr );1.1702 } else {1.1703 // Note: we use sh4r.pc for the calc as we could be running at a1.1704 // different virtual address than the translation was done with,1.1705 // but we can safely assume that the low bits are the same.1.1706 - load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );1.1707 - ADD_sh4r_r32( R_PC, R_EAX );1.1708 - MEM_READ_LONG( R_EAX, R_EAX );1.1709 + load_imm32( REG_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );1.1710 + ADDL_rbpdisp_r32( R_PC, REG_EAX );1.1711 + MEM_READ_LONG( REG_EAX, REG_EAX );1.1712 sh4_x86.tstate = TSTATE_NONE;1.1713 }1.1714 - store_reg( R_EAX, Rn );1.1715 + store_reg( REG_EAX, Rn );1.1716 }1.1717 :}1.1718 MOV.L @(disp, Rm), Rn {:1.1719 COUNT_INST(I_MOVL);1.1720 - load_reg( R_EAX, Rm );1.1721 - ADD_imm8s_r32( disp, R_EAX );1.1722 - check_ralign32( R_EAX );1.1723 - MEM_READ_LONG( R_EAX, R_EAX );1.1724 - store_reg( R_EAX, Rn );1.1725 + load_reg( REG_EAX, Rm );1.1726 + ADDL_imms_r32( disp, REG_EAX );1.1727 + check_ralign32( REG_EAX );1.1728 + MEM_READ_LONG( REG_EAX, REG_EAX );1.1729 + store_reg( REG_EAX, Rn );1.1730 sh4_x86.tstate = TSTATE_NONE;1.1731 :}1.1732 MOV.W Rm, @Rn {:1.1733 COUNT_INST(I_MOVW);1.1734 - load_reg( R_EAX, Rn );1.1735 - check_walign16( R_EAX );1.1736 - load_reg( R_EDX, Rm );1.1737 - MEM_WRITE_WORD( R_EAX, R_EDX );1.1738 + load_reg( REG_EAX, Rn );1.1739 + check_walign16( REG_EAX );1.1740 + load_reg( REG_EDX, Rm );1.1741 + MEM_WRITE_WORD( REG_EAX, REG_EDX );1.1742 sh4_x86.tstate = TSTATE_NONE;1.1743 :}1.1744 MOV.W Rm, @-Rn {:1.1745 COUNT_INST(I_MOVW);1.1746 - load_reg( R_EAX, Rn );1.1747 - check_walign16( R_EAX );1.1748 - LEA_r32disp8_r32( R_EAX, -2, R_EAX );1.1749 - load_reg( R_EDX, Rm );1.1750 - MEM_WRITE_WORD( R_EAX, R_EDX );1.1751 - ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );1.1752 + load_reg( REG_EAX, Rn );1.1753 + check_walign16( REG_EAX );1.1754 + LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );1.1755 + load_reg( REG_EDX, Rm );1.1756 + MEM_WRITE_WORD( REG_EAX, REG_EDX );1.1757 + ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );1.1758 sh4_x86.tstate = TSTATE_NONE;1.1759 :}1.1760 MOV.W Rm, @(R0, Rn) {:1.1761 COUNT_INST(I_MOVW);1.1762 - load_reg( R_EAX, 0 );1.1763 - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );1.1764 - check_walign16( R_EAX );1.1765 - load_reg( R_EDX, Rm );1.1766 - MEM_WRITE_WORD( R_EAX, R_EDX );1.1767 + load_reg( REG_EAX, 0 );1.1768 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );1.1769 + check_walign16( REG_EAX );1.1770 + load_reg( REG_EDX, Rm );1.1771 + MEM_WRITE_WORD( REG_EAX, REG_EDX );1.1772 sh4_x86.tstate = TSTATE_NONE;1.1773 :}1.1774 MOV.W R0, @(disp, GBR) {:1.1775 COUNT_INST(I_MOVW);1.1776 - load_spreg( R_EAX, R_GBR );1.1777 - ADD_imm32_r32( disp, R_EAX );1.1778 - check_walign16( R_EAX );1.1779 - load_reg( R_EDX, 0 );1.1780 - MEM_WRITE_WORD( R_EAX, R_EDX );1.1781 + load_spreg( REG_EAX, R_GBR );1.1782 + ADDL_imms_r32( disp, REG_EAX );1.1783 + check_walign16( REG_EAX );1.1784 + load_reg( REG_EDX, 0 );1.1785 + MEM_WRITE_WORD( REG_EAX, REG_EDX );1.1786 sh4_x86.tstate = TSTATE_NONE;1.1787 :}1.1788 MOV.W R0, @(disp, Rn) {:1.1789 COUNT_INST(I_MOVW);1.1790 - load_reg( R_EAX, Rn );1.1791 - ADD_imm32_r32( disp, R_EAX );1.1792 - check_walign16( R_EAX );1.1793 - load_reg( R_EDX, 0 );1.1794 - MEM_WRITE_WORD( R_EAX, R_EDX );1.1795 + load_reg( REG_EAX, Rn );1.1796 + ADDL_imms_r32( disp, REG_EAX );1.1797 + check_walign16( REG_EAX );1.1798 + load_reg( REG_EDX, 0 );1.1799 + MEM_WRITE_WORD( REG_EAX, REG_EDX );1.1800 sh4_x86.tstate = TSTATE_NONE;1.1801 :}1.1802 MOV.W @Rm, Rn {:1.1803 COUNT_INST(I_MOVW);1.1804 - load_reg( R_EAX, Rm );1.1805 - check_ralign16( R_EAX );1.1806 - MEM_READ_WORD( R_EAX, R_EAX );1.1807 - store_reg( R_EAX, Rn );1.1808 + load_reg( REG_EAX, Rm );1.1809 + check_ralign16( REG_EAX );1.1810 + MEM_READ_WORD( REG_EAX, REG_EAX );1.1811 + store_reg( REG_EAX, Rn );1.1812 sh4_x86.tstate = TSTATE_NONE;1.1813 :}1.1814 MOV.W @Rm+, Rn {:1.1815 COUNT_INST(I_MOVW);1.1816 - load_reg( R_EAX, Rm );1.1817 - check_ralign16( R_EAX );1.1818 - MEM_READ_WORD( R_EAX, R_EAX );1.1819 + load_reg( REG_EAX, Rm );1.1820 + check_ralign16( REG_EAX );1.1821 + MEM_READ_WORD( REG_EAX, REG_EAX );1.1822 if( Rm != Rn ) {1.1823 - ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );1.1824 + ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );1.1825 }1.1826 - store_reg( R_EAX, Rn );1.1827 + store_reg( REG_EAX, Rn );1.1828 sh4_x86.tstate = TSTATE_NONE;1.1829 :}1.1830 MOV.W @(R0, Rm), Rn {:1.1831 COUNT_INST(I_MOVW);1.1832 - load_reg( R_EAX, 0 );1.1833 - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );1.1834 - check_ralign16( R_EAX );1.1835 - MEM_READ_WORD( R_EAX, R_EAX );1.1836 - store_reg( R_EAX, Rn );1.1837 + load_reg( REG_EAX, 0 );1.1838 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );1.1839 + check_ralign16( REG_EAX );1.1840 + MEM_READ_WORD( REG_EAX, REG_EAX );1.1841 + store_reg( REG_EAX, Rn );1.1842 sh4_x86.tstate = TSTATE_NONE;1.1843 :}1.1844 MOV.W @(disp, GBR), R0 {:1.1845 COUNT_INST(I_MOVW);1.1846 - load_spreg( R_EAX, R_GBR );1.1847 - ADD_imm32_r32( disp, R_EAX );1.1848 - check_ralign16( R_EAX );1.1849 - MEM_READ_WORD( R_EAX, R_EAX );1.1850 - store_reg( R_EAX, 0 );1.1851 + load_spreg( REG_EAX, R_GBR );1.1852 + ADDL_imms_r32( disp, REG_EAX );1.1853 + check_ralign16( REG_EAX );1.1854 + MEM_READ_WORD( REG_EAX, REG_EAX );1.1855 + store_reg( REG_EAX, 0 );1.1856 sh4_x86.tstate = TSTATE_NONE;1.1857 :}1.1858 MOV.W @(disp, PC), Rn {:1.1859 @@ -1420,24 +1423,24 @@1.1860 uint32_t target = pc + disp + 4;1.1861 if( IS_IN_ICACHE(target) ) {1.1862 sh4ptr_t ptr = GET_ICACHE_PTR(target);1.1863 - MOV_moff32_EAX( ptr );1.1864 - MOVSX_r16_r32( R_EAX, R_EAX );1.1865 + MOVL_moffptr_eax( ptr );1.1866 + MOVSXL_r16_r32( REG_EAX, REG_EAX );1.1867 } else {1.1868 - load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );1.1869 - ADD_sh4r_r32( R_PC, R_EAX );1.1870 - MEM_READ_WORD( R_EAX, R_EAX );1.1871 + load_imm32( REG_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );1.1872 + ADDL_rbpdisp_r32( R_PC, REG_EAX );1.1873 + MEM_READ_WORD( REG_EAX, REG_EAX );1.1874 sh4_x86.tstate = TSTATE_NONE;1.1875 }1.1876 - store_reg( R_EAX, Rn );1.1877 + store_reg( REG_EAX, Rn );1.1878 }1.1879 :}1.1880 MOV.W @(disp, Rm), R0 {:1.1881 COUNT_INST(I_MOVW);1.1882 - load_reg( R_EAX, Rm );1.1883 - ADD_imm32_r32( disp, R_EAX );1.1884 - check_ralign16( R_EAX );1.1885 - MEM_READ_WORD( R_EAX, R_EAX );1.1886 - store_reg( R_EAX, 0 );1.1887 + load_reg( REG_EAX, Rm );1.1888 + ADDL_imms_r32( disp, REG_EAX );1.1889 + check_ralign16( REG_EAX );1.1890 + MEM_READ_WORD( REG_EAX, REG_EAX );1.1891 + store_reg( REG_EAX, 0 );1.1892 sh4_x86.tstate = TSTATE_NONE;1.1893 :}1.1894 MOVA @(disp, PC), R0 {:1.1895 @@ -1445,18 +1448,18 @@1.1896 if( sh4_x86.in_delay_slot ) {1.1897 SLOTILLEGAL();1.1898 } else {1.1899 - load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );1.1900 - ADD_sh4r_r32( R_PC, R_ECX );1.1901 - store_reg( R_ECX, 0 );1.1902 + load_imm32( REG_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );1.1903 + ADDL_rbpdisp_r32( R_PC, REG_ECX );1.1904 + store_reg( REG_ECX, 0 );1.1905 sh4_x86.tstate = TSTATE_NONE;1.1906 }1.1907 :}1.1908 MOVCA.L R0, @Rn {:1.1909 COUNT_INST(I_MOVCA);1.1910 - load_reg( R_EAX, Rn );1.1911 - check_walign32( R_EAX );1.1912 - load_reg( R_EDX, 0 );1.1913 - MEM_WRITE_LONG( R_EAX, R_EDX );1.1914 + load_reg( REG_EAX, Rn );1.1915 + check_walign32( REG_EAX );1.1916 + load_reg( REG_EDX, 0 );1.1917 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.1918 sh4_x86.tstate = TSTATE_NONE;1.1919 :}1.1921 @@ -1467,7 +1470,7 @@1.1922 SLOTILLEGAL();1.1923 } else {1.1924 sh4vma_t target = disp + pc + 4;1.1925 - JT_rel8( nottaken );1.1926 + JT_label( nottaken );1.1927 exit_block_rel(target, pc+2 );1.1928 JMP_TARGET(nottaken);1.1929 return 2;1.1930 @@ -1480,22 +1483,23 @@1.1931 } else {1.1932 sh4_x86.in_delay_slot = DELAY_PC;1.1933 if( UNTRANSLATABLE(pc+2) ) {1.1934 - load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );1.1935 - JT_rel8(nottaken);1.1936 - ADD_imm32_r32( disp, R_EAX );1.1937 + load_imm32( REG_EAX, pc + 4 - sh4_x86.block_start_pc );1.1938 + JT_label(nottaken);1.1939 + ADDL_imms_r32( disp, REG_EAX );1.1940 JMP_TARGET(nottaken);1.1941 - ADD_sh4r_r32( R_PC, R_EAX );1.1942 - store_spreg( R_EAX, R_NEW_PC );1.1943 + ADDL_rbpdisp_r32( R_PC, REG_EAX );1.1944 + store_spreg( REG_EAX, R_NEW_PC );1.1945 exit_block_emu(pc+2);1.1946 sh4_x86.branch_taken = TRUE;1.1947 return 2;1.1948 } else {1.1949 if( sh4_x86.tstate == TSTATE_NONE ) {1.1950 - CMP_imm8s_sh4r( 1, R_T );1.1951 + CMPL_imms_rbpdisp( 1, R_T );1.1952 sh4_x86.tstate = TSTATE_E;1.1953 }1.1954 sh4vma_t target = disp + pc + 4;1.1955 - OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel321.1956 + JCC_cc_rel32(sh4_x86.tstate,0);1.1957 + uint32_t *patch = ((uint32_t *)xlat_output)-1;1.1958 int save_tstate = sh4_x86.tstate;1.1959 sh4_translate_instruction(pc+2);1.1960 exit_block_rel( target, pc+4 );1.1961 @@ -1516,9 +1520,9 @@1.1962 sh4_x86.in_delay_slot = DELAY_PC;1.1963 sh4_x86.branch_taken = TRUE;1.1964 if( UNTRANSLATABLE(pc+2) ) {1.1965 - load_spreg( R_EAX, R_PC );1.1966 - ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );1.1967 - store_spreg( R_EAX, R_NEW_PC );1.1968 + load_spreg( REG_EAX, R_PC );1.1969 + ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );1.1970 + store_spreg( REG_EAX, R_NEW_PC );1.1971 exit_block_emu(pc+2);1.1972 return 2;1.1973 } else {1.1974 @@ -1533,10 +1537,10 @@1.1975 if( sh4_x86.in_delay_slot ) {1.1976 SLOTILLEGAL();1.1977 } else {1.1978 - load_spreg( R_EAX, R_PC );1.1979 - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );1.1980 - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );1.1981 - store_spreg( R_EAX, R_NEW_PC );1.1982 + load_spreg( REG_EAX, R_PC );1.1983 + ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );1.1984 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );1.1985 + store_spreg( REG_EAX, R_NEW_PC );1.1986 sh4_x86.in_delay_slot = DELAY_PC;1.1987 sh4_x86.tstate = TSTATE_NONE;1.1988 sh4_x86.branch_taken = TRUE;1.1989 @@ -1555,15 +1559,15 @@1.1990 if( sh4_x86.in_delay_slot ) {1.1991 SLOTILLEGAL();1.1992 } else {1.1993 - load_spreg( R_EAX, R_PC );1.1994 - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );1.1995 - store_spreg( R_EAX, R_PR );1.1996 + load_spreg( REG_EAX, R_PC );1.1997 + ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );1.1998 + store_spreg( REG_EAX, R_PR );1.1999 sh4_x86.in_delay_slot = DELAY_PC;1.2000 sh4_x86.branch_taken = TRUE;1.2001 sh4_x86.tstate = TSTATE_NONE;1.2002 if( UNTRANSLATABLE(pc+2) ) {1.2003 - ADD_imm32_r32( disp, R_EAX );1.2004 - store_spreg( R_EAX, R_NEW_PC );1.2005 + ADDL_imms_r32( disp, REG_EAX );1.2006 + store_spreg( REG_EAX, R_NEW_PC );1.2007 exit_block_emu(pc+2);1.2008 return 2;1.2009 } else {1.2010 @@ -1578,11 +1582,11 @@1.2011 if( sh4_x86.in_delay_slot ) {1.2012 SLOTILLEGAL();1.2013 } else {1.2014 - load_spreg( R_EAX, R_PC );1.2015 - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );1.2016 - store_spreg( R_EAX, R_PR );1.2017 - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );1.2018 - store_spreg( R_EAX, R_NEW_PC );1.2019 + load_spreg( REG_EAX, R_PC );1.2020 + ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );1.2021 + store_spreg( REG_EAX, R_PR );1.2022 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );1.2023 + store_spreg( REG_EAX, R_NEW_PC );1.2025 sh4_x86.in_delay_slot = DELAY_PC;1.2026 sh4_x86.tstate = TSTATE_NONE;1.2027 @@ -1603,7 +1607,7 @@1.2028 SLOTILLEGAL();1.2029 } else {1.2030 sh4vma_t target = disp + pc + 4;1.2031 - JF_rel8( nottaken );1.2032 + JF_label( nottaken );1.2033 exit_block_rel(target, pc+2 );1.2034 JMP_TARGET(nottaken);1.2035 return 2;1.2036 @@ -1616,21 +1620,23 @@1.2037 } else {1.2038 sh4_x86.in_delay_slot = DELAY_PC;1.2039 if( UNTRANSLATABLE(pc+2) ) {1.2040 - load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );1.2041 - JF_rel8(nottaken);1.2042 - ADD_imm32_r32( disp, R_EAX );1.2043 + load_imm32( REG_EAX, pc + 4 - sh4_x86.block_start_pc );1.2044 + JF_label(nottaken);1.2045 + ADDL_imms_r32( disp, REG_EAX );1.2046 JMP_TARGET(nottaken);1.2047 - ADD_sh4r_r32( R_PC, R_EAX );1.2048 - store_spreg( R_EAX, R_NEW_PC );1.2049 + ADDL_rbpdisp_r32( R_PC, REG_EAX );1.2050 + store_spreg( REG_EAX, R_NEW_PC );1.2051 exit_block_emu(pc+2);1.2052 sh4_x86.branch_taken = TRUE;1.2053 return 2;1.2054 } else {1.2055 if( sh4_x86.tstate == TSTATE_NONE ) {1.2056 - CMP_imm8s_sh4r( 1, R_T );1.2057 + CMPL_imms_rbpdisp( 1, R_T );1.2058 sh4_x86.tstate = TSTATE_E;1.2059 }1.2060 - OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel321.2061 + JCC_cc_rel32(sh4_x86.tstate^1,0);1.2062 + uint32_t *patch = ((uint32_t *)xlat_output)-1;1.2063 +1.2064 int save_tstate = sh4_x86.tstate;1.2065 sh4_translate_instruction(pc+2);1.2066 exit_block_rel( disp + pc + 4, pc+4 );1.2067 @@ -1647,8 +1653,8 @@1.2068 if( sh4_x86.in_delay_slot ) {1.2069 SLOTILLEGAL();1.2070 } else {1.2071 - load_reg( R_ECX, Rn );1.2072 - store_spreg( R_ECX, R_NEW_PC );1.2073 + load_reg( REG_ECX, Rn );1.2074 + store_spreg( REG_ECX, R_NEW_PC );1.2075 sh4_x86.in_delay_slot = DELAY_PC;1.2076 sh4_x86.branch_taken = TRUE;1.2077 if( UNTRANSLATABLE(pc+2) ) {1.2078 @@ -1666,11 +1672,11 @@1.2079 if( sh4_x86.in_delay_slot ) {1.2080 SLOTILLEGAL();1.2081 } else {1.2082 - load_spreg( R_EAX, R_PC );1.2083 - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );1.2084 - store_spreg( R_EAX, R_PR );1.2085 - load_reg( R_ECX, Rn );1.2086 - store_spreg( R_ECX, R_NEW_PC );1.2087 + load_spreg( REG_EAX, R_PC );1.2088 + ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );1.2089 + store_spreg( REG_EAX, R_PR );1.2090 + load_reg( REG_ECX, Rn );1.2091 + store_spreg( REG_ECX, R_NEW_PC );1.2092 sh4_x86.in_delay_slot = DELAY_PC;1.2093 sh4_x86.branch_taken = TRUE;1.2094 sh4_x86.tstate = TSTATE_NONE;1.2095 @@ -1690,10 +1696,10 @@1.2096 SLOTILLEGAL();1.2097 } else {1.2098 check_priv();1.2099 - load_spreg( R_ECX, R_SPC );1.2100 - store_spreg( R_ECX, R_NEW_PC );1.2101 - load_spreg( R_EAX, R_SSR );1.2102 - call_func1( sh4_write_sr, R_EAX );1.2103 + load_spreg( REG_ECX, R_SPC );1.2104 + store_spreg( REG_ECX, R_NEW_PC );1.2105 + load_spreg( REG_EAX, R_SSR );1.2106 + call_func1( sh4_write_sr, REG_EAX );1.2107 sh4_x86.in_delay_slot = DELAY_PC;1.2108 sh4_x86.fpuen_checked = FALSE;1.2109 sh4_x86.tstate = TSTATE_NONE;1.2110 @@ -1713,8 +1719,8 @@1.2111 if( sh4_x86.in_delay_slot ) {1.2112 SLOTILLEGAL();1.2113 } else {1.2114 - load_spreg( R_ECX, R_PR );1.2115 - store_spreg( R_ECX, R_NEW_PC );1.2116 + load_spreg( REG_ECX, R_PR );1.2117 + store_spreg( REG_ECX, R_NEW_PC );1.2118 sh4_x86.in_delay_slot = DELAY_PC;1.2119 sh4_x86.branch_taken = TRUE;1.2120 if( UNTRANSLATABLE(pc+2) ) {1.2121 @@ -1732,10 +1738,10 @@1.2122 if( sh4_x86.in_delay_slot ) {1.2123 SLOTILLEGAL();1.2124 } else {1.2125 - load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc ); // 51.2126 - ADD_r32_sh4r( R_ECX, R_PC );1.2127 - load_imm32( R_EAX, imm );1.2128 - call_func1( sh4_raise_trap, R_EAX );1.2129 + load_imm32( REG_ECX, pc+2 - sh4_x86.block_start_pc ); // 51.2130 + ADDL_r32_rbpdisp( REG_ECX, R_PC );1.2131 + load_imm32( REG_EAX, imm );1.2132 + call_func1( sh4_raise_trap, REG_EAX );1.2133 sh4_x86.tstate = TSTATE_NONE;1.2134 exit_block_pcset(pc+2);1.2135 sh4_x86.branch_taken = TRUE;1.2136 @@ -1754,15 +1760,15 @@1.2138 CLRMAC {:1.2139 COUNT_INST(I_CLRMAC);1.2140 - XOR_r32_r32(R_EAX, R_EAX);1.2141 - store_spreg( R_EAX, R_MACL );1.2142 - store_spreg( R_EAX, R_MACH );1.2143 + XORL_r32_r32(REG_EAX, REG_EAX);1.2144 + store_spreg( REG_EAX, R_MACL );1.2145 + store_spreg( REG_EAX, R_MACH );1.2146 sh4_x86.tstate = TSTATE_NONE;1.2147 :}1.2148 CLRS {:1.2149 COUNT_INST(I_CLRS);1.2150 CLC();1.2151 - SETC_sh4r(R_S);1.2152 + SETCCB_cc_rbpdisp(X86_COND_C, R_S);1.2153 sh4_x86.tstate = TSTATE_NONE;1.2154 :}1.2155 CLRT {:1.2156 @@ -1774,7 +1780,7 @@1.2157 SETS {:1.2158 COUNT_INST(I_SETS);1.2159 STC();1.2160 - SETC_sh4r(R_S);1.2161 + SETCCB_cc_rbpdisp(X86_COND_C, R_S);1.2162 sh4_x86.tstate = TSTATE_NONE;1.2163 :}1.2164 SETT {:1.2165 @@ -1789,136 +1795,136 @@1.2166 COUNT_INST(I_FMOV1);1.2167 check_fpuen();1.2168 if( sh4_x86.double_size ) {1.2169 - load_dr0( R_EAX, FRm );1.2170 - load_dr1( R_ECX, FRm );1.2171 - store_dr0( R_EAX, FRn );1.2172 - store_dr1( R_ECX, FRn );1.2173 + load_dr0( REG_EAX, FRm );1.2174 + load_dr1( REG_ECX, FRm );1.2175 + store_dr0( REG_EAX, FRn );1.2176 + store_dr1( REG_ECX, FRn );1.2177 } else {1.2178 - load_fr( R_EAX, FRm ); // SZ=0 branch1.2179 - store_fr( R_EAX, FRn );1.2180 + load_fr( REG_EAX, FRm ); // SZ=0 branch1.2181 + store_fr( REG_EAX, FRn );1.2182 }1.2183 :}1.2184 FMOV FRm, @Rn {:1.2185 COUNT_INST(I_FMOV2);1.2186 check_fpuen();1.2187 - load_reg( R_EAX, Rn );1.2188 + load_reg( REG_EAX, Rn );1.2189 if( sh4_x86.double_size ) {1.2190 - check_walign64( R_EAX );1.2191 - load_dr0( R_EDX, FRm );1.2192 - MEM_WRITE_LONG( R_EAX, R_EDX );1.2193 - load_reg( R_EAX, Rn );1.2194 - LEA_r32disp8_r32( R_EAX, 4, R_EAX );1.2195 - load_dr1( R_EDX, FRm );1.2196 - MEM_WRITE_LONG( R_EAX, R_EDX );1.2197 + check_walign64( REG_EAX );1.2198 + load_dr0( REG_EDX, FRm );1.2199 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.2200 + load_reg( REG_EAX, Rn );1.2201 + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );1.2202 + load_dr1( REG_EDX, FRm );1.2203 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.2204 } else {1.2205 - check_walign32( R_EAX );1.2206 - load_fr( R_EDX, FRm );1.2207 - MEM_WRITE_LONG( R_EAX, R_EDX );1.2208 + check_walign32( REG_EAX );1.2209 + load_fr( REG_EDX, FRm );1.2210 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.2211 }1.2212 sh4_x86.tstate = TSTATE_NONE;1.2213 :}1.2214 FMOV @Rm, FRn {:1.2215 COUNT_INST(I_FMOV5);1.2216 check_fpuen();1.2217 - load_reg( R_EAX, Rm );1.2218 + load_reg( REG_EAX, Rm );1.2219 if( sh4_x86.double_size ) {1.2220 - check_ralign64( R_EAX );1.2221 - MEM_READ_LONG( R_EAX, R_EAX );1.2222 - store_dr0( R_EAX, FRn );1.2223 - load_reg( R_EAX, Rm );1.2224 - LEA_r32disp8_r32( R_EAX, 4, R_EAX );1.2225 - MEM_READ_LONG( R_EAX, R_EAX );1.2226 - store_dr1( R_EAX, FRn );1.2227 + check_ralign64( REG_EAX );1.2228 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2229 + store_dr0( REG_EAX, FRn );1.2230 + load_reg( REG_EAX, Rm );1.2231 + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );1.2232 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2233 + store_dr1( REG_EAX, FRn );1.2234 } else {1.2235 - check_ralign32( R_EAX );1.2236 - MEM_READ_LONG( R_EAX, R_EAX );1.2237 - store_fr( R_EAX, FRn );1.2238 + check_ralign32( REG_EAX );1.2239 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2240 + store_fr( REG_EAX, FRn );1.2241 }1.2242 sh4_x86.tstate = TSTATE_NONE;1.2243 :}1.2244 FMOV FRm, @-Rn {:1.2245 COUNT_INST(I_FMOV3);1.2246 check_fpuen();1.2247 - load_reg( R_EAX, Rn );1.2248 + load_reg( REG_EAX, Rn );1.2249 if( sh4_x86.double_size ) {1.2250 - check_walign64( R_EAX );1.2251 - LEA_r32disp8_r32( R_EAX, -8, R_EAX );1.2252 - load_dr0( R_EDX, FRm );1.2253 - MEM_WRITE_LONG( R_EAX, R_EDX );1.2254 - load_reg( R_EAX, Rn );1.2255 - LEA_r32disp8_r32( R_EAX, -4, R_EAX );1.2256 - load_dr1( R_EDX, FRm );1.2257 - MEM_WRITE_LONG( R_EAX, R_EDX );1.2258 - ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));1.2259 + check_walign64( REG_EAX );1.2260 + LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );1.2261 + load_dr0( REG_EDX, FRm );1.2262 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.2263 + load_reg( REG_EAX, Rn );1.2264 + LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );1.2265 + load_dr1( REG_EDX, FRm );1.2266 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.2267 + ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));1.2268 } else {1.2269 - check_walign32( R_EAX );1.2270 - LEA_r32disp8_r32( R_EAX, -4, R_EAX );1.2271 - load_fr( R_EDX, FRm );1.2272 - MEM_WRITE_LONG( R_EAX, R_EDX );1.2273 - ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));1.2274 + check_walign32( REG_EAX );1.2275 + LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );1.2276 + load_fr( REG_EDX, FRm );1.2277 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.2278 + ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));1.2279 }1.2280 sh4_x86.tstate = TSTATE_NONE;1.2281 :}1.2282 FMOV @Rm+, FRn {:1.2283 COUNT_INST(I_FMOV6);1.2284 check_fpuen();1.2285 - load_reg( R_EAX, Rm );1.2286 + load_reg( REG_EAX, Rm );1.2287 if( sh4_x86.double_size ) {1.2288 - check_ralign64( R_EAX );1.2289 - MEM_READ_LONG( R_EAX, R_EAX );1.2290 - store_dr0( R_EAX, FRn );1.2291 - load_reg( R_EAX, Rm );1.2292 - LEA_r32disp8_r32( R_EAX, 4, R_EAX );1.2293 - MEM_READ_LONG( R_EAX, R_EAX );1.2294 - store_dr1( R_EAX, FRn );1.2295 - ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );1.2296 + check_ralign64( REG_EAX );1.2297 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2298 + store_dr0( REG_EAX, FRn );1.2299 + load_reg( REG_EAX, Rm );1.2300 + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );1.2301 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2302 + store_dr1( REG_EAX, FRn );1.2303 + ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );1.2304 } else {1.2305 - check_ralign32( R_EAX );1.2306 - MEM_READ_LONG( R_EAX, R_EAX );1.2307 - store_fr( R_EAX, FRn );1.2308 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2309 + check_ralign32( REG_EAX );1.2310 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2311 + store_fr( REG_EAX, FRn );1.2312 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2313 }1.2314 sh4_x86.tstate = TSTATE_NONE;1.2315 :}1.2316 FMOV FRm, @(R0, Rn) {:1.2317 COUNT_INST(I_FMOV4);1.2318 check_fpuen();1.2319 - load_reg( R_EAX, Rn );1.2320 - ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );1.2321 + load_reg( REG_EAX, Rn );1.2322 + ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );1.2323 if( sh4_x86.double_size ) {1.2324 - check_walign64( R_EAX );1.2325 - load_dr0( R_EDX, FRm );1.2326 - MEM_WRITE_LONG( R_EAX, R_EDX );1.2327 - load_reg( R_EAX, Rn );1.2328 - ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );1.2329 - LEA_r32disp8_r32( R_EAX, 4, R_EAX );1.2330 - load_dr1( R_EDX, FRm );1.2331 - MEM_WRITE_LONG( R_EAX, R_EDX );1.2332 + check_walign64( REG_EAX );1.2333 + load_dr0( REG_EDX, FRm );1.2334 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.2335 + load_reg( REG_EAX, Rn );1.2336 + ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );1.2337 + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );1.2338 + load_dr1( REG_EDX, FRm );1.2339 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.2340 } else {1.2341 - check_walign32( R_EAX );1.2342 - load_fr( R_EDX, FRm );1.2343 - MEM_WRITE_LONG( R_EAX, R_EDX ); // 121.2344 + check_walign32( REG_EAX );1.2345 + load_fr( REG_EDX, FRm );1.2346 + MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 121.2347 }1.2348 sh4_x86.tstate = TSTATE_NONE;1.2349 :}1.2350 FMOV @(R0, Rm), FRn {:1.2351 COUNT_INST(I_FMOV7);1.2352 check_fpuen();1.2353 - load_reg( R_EAX, Rm );1.2354 - ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );1.2355 + load_reg( REG_EAX, Rm );1.2356 + ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );1.2357 if( sh4_x86.double_size ) {1.2358 - check_ralign64( R_EAX );1.2359 - MEM_READ_LONG( R_EAX, R_EAX );1.2360 - store_dr0( R_EAX, FRn );1.2361 - load_reg( R_EAX, Rm );1.2362 - ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );1.2363 - LEA_r32disp8_r32( R_EAX, 4, R_EAX );1.2364 - MEM_READ_LONG( R_EAX, R_EAX );1.2365 - store_dr1( R_EAX, FRn );1.2366 + check_ralign64( REG_EAX );1.2367 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2368 + store_dr0( REG_EAX, FRn );1.2369 + load_reg( REG_EAX, Rm );1.2370 + ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );1.2371 + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );1.2372 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2373 + store_dr1( REG_EAX, FRn );1.2374 } else {1.2375 - check_ralign32( R_EAX );1.2376 - MEM_READ_LONG( R_EAX, R_EAX );1.2377 - store_fr( R_EAX, FRn );1.2378 + check_ralign32( REG_EAX );1.2379 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2380 + store_fr( REG_EAX, FRn );1.2381 }1.2382 sh4_x86.tstate = TSTATE_NONE;1.2383 :}1.2384 @@ -1926,8 +1932,8 @@1.2385 COUNT_INST(I_FLDI0);1.2386 check_fpuen();1.2387 if( sh4_x86.double_prec == 0 ) {1.2388 - XOR_r32_r32( R_EAX, R_EAX );1.2389 - store_fr( R_EAX, FRn );1.2390 + XORL_r32_r32( REG_EAX, REG_EAX );1.2391 + store_fr( REG_EAX, FRn );1.2392 }1.2393 sh4_x86.tstate = TSTATE_NONE;1.2394 :}1.2395 @@ -1935,15 +1941,15 @@1.2396 COUNT_INST(I_FLDI1);1.2397 check_fpuen();1.2398 if( sh4_x86.double_prec == 0 ) {1.2399 - load_imm32(R_EAX, 0x3F800000);1.2400 - store_fr( R_EAX, FRn );1.2401 + load_imm32(REG_EAX, 0x3F800000);1.2402 + store_fr( REG_EAX, FRn );1.2403 }1.2404 :}1.2406 FLOAT FPUL, FRn {:1.2407 COUNT_INST(I_FLOAT);1.2408 check_fpuen();1.2409 - FILD_sh4r(R_FPUL);1.2410 + FILD_rbpdisp(R_FPUL);1.2411 if( sh4_x86.double_prec ) {1.2412 pop_dr( FRn );1.2413 } else {1.2414 @@ -1958,26 +1964,26 @@1.2415 } else {1.2416 push_fr( FRm );1.2417 }1.2418 - load_ptr( R_ECX, &max_int );1.2419 - FILD_r32ind( R_ECX );1.2420 + load_ptr( REG_ECX, &max_int );1.2421 + FILD_r32disp( REG_ECX, 0 );1.2422 FCOMIP_st(1);1.2423 - JNA_rel8( sat );1.2424 - load_ptr( R_ECX, &min_int ); // 51.2425 - FILD_r32ind( R_ECX ); // 21.2426 + JNA_label( sat );1.2427 + load_ptr( REG_ECX, &min_int ); // 51.2428 + FILD_r32disp( REG_ECX, 0 ); // 21.2429 FCOMIP_st(1); // 21.2430 - JAE_rel8( sat2 ); // 21.2431 - load_ptr( R_EAX, &save_fcw );1.2432 - FNSTCW_r32ind( R_EAX );1.2433 - load_ptr( R_EDX, &trunc_fcw );1.2434 - FLDCW_r32ind( R_EDX );1.2435 - FISTP_sh4r(R_FPUL); // 31.2436 - FLDCW_r32ind( R_EAX );1.2437 - JMP_rel8(end); // 21.2438 + JAE_label( sat2 ); // 21.2439 + load_ptr( REG_EAX, &save_fcw );1.2440 + FNSTCW_r32disp( REG_EAX, 0 );1.2441 + load_ptr( REG_EDX, &trunc_fcw );1.2442 + FLDCW_r32disp( REG_EDX, 0 );1.2443 + FISTP_rbpdisp(R_FPUL); // 31.2444 + FLDCW_r32disp( REG_EAX, 0 );1.2445 + JMP_label(end); // 21.2447 JMP_TARGET(sat);1.2448 JMP_TARGET(sat2);1.2449 - MOV_r32ind_r32( R_ECX, R_ECX ); // 21.2450 - store_spreg( R_ECX, R_FPUL );1.2451 + MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 21.2452 + store_spreg( REG_ECX, R_FPUL );1.2453 FPOP_st();1.2454 JMP_TARGET(end);1.2455 sh4_x86.tstate = TSTATE_NONE;1.2456 @@ -1985,14 +1991,14 @@1.2457 FLDS FRm, FPUL {:1.2458 COUNT_INST(I_FLDS);1.2459 check_fpuen();1.2460 - load_fr( R_EAX, FRm );1.2461 - store_spreg( R_EAX, R_FPUL );1.2462 + load_fr( REG_EAX, FRm );1.2463 + store_spreg( REG_EAX, R_FPUL );1.2464 :}1.2465 FSTS FPUL, FRn {:1.2466 COUNT_INST(I_FSTS);1.2467 check_fpuen();1.2468 - load_spreg( R_EAX, R_FPUL );1.2469 - store_fr( R_EAX, FRn );1.2470 + load_spreg( REG_EAX, R_FPUL );1.2471 + store_fr( REG_EAX, FRn );1.2472 :}1.2473 FCNVDS FRm, FPUL {:1.2474 COUNT_INST(I_FCNVDS);1.2475 @@ -2178,9 +2184,9 @@1.2476 COUNT_INST(I_FSCA);1.2477 check_fpuen();1.2478 if( sh4_x86.double_prec == 0 ) {1.2479 - LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );1.2480 - load_spreg( R_EAX, R_FPUL );1.2481 - call_func2( sh4_fsca, R_EAX, R_EDX );1.2482 + LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );1.2483 + load_spreg( REG_EAX, R_FPUL );1.2484 + call_func2( sh4_fsca, REG_EAX, REG_EDX );1.2485 }1.2486 sh4_x86.tstate = TSTATE_NONE;1.2487 :}1.2488 @@ -2189,11 +2195,11 @@1.2489 check_fpuen();1.2490 if( sh4_x86.double_prec == 0 ) {1.2491 if( sh4_x86.sse3_enabled ) {1.2492 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );1.2493 - MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );1.2494 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );1.2495 + MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );1.2496 HADDPS_xmm_xmm( 4, 4 );1.2497 HADDPS_xmm_xmm( 4, 4 );1.2498 - MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );1.2499 + MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );1.2500 } else {1.2501 push_fr( FVm<<2 );1.2502 push_fr( FVn<<2 );1.2503 @@ -2219,15 +2225,15 @@1.2504 check_fpuen();1.2505 if( sh4_x86.double_prec == 0 ) {1.2506 if( sh4_x86.sse3_enabled ) {1.2507 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1 M0 M3 M21.2508 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5 M4 M7 M61.2509 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9 M8 M11 M101.2510 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M141.2511 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1 M0 M3 M21.2512 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5 M4 M7 M61.2513 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9 M8 M11 M101.2514 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M141.2516 - MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V31.2517 - MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V21.2518 - MOVAPS_xmm_xmm( 4, 6 );1.2519 - MOVAPS_xmm_xmm( 5, 7 );1.2520 + MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V31.2521 + MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V21.2522 + MOV_xmm_xmm( 4, 6 );1.2523 + MOV_xmm_xmm( 5, 7 );1.2524 MOVLHPS_xmm_xmm( 4, 4 ); // V1 V1 V1 V11.2525 MOVHLPS_xmm_xmm( 6, 6 ); // V3 V3 V3 V31.2526 MOVLHPS_xmm_xmm( 5, 5 ); // V0 V0 V0 V01.2527 @@ -2239,10 +2245,10 @@1.2528 ADDPS_xmm_xmm( 5, 4 );1.2529 ADDPS_xmm_xmm( 7, 6 );1.2530 ADDPS_xmm_xmm( 6, 4 );1.2531 - MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );1.2532 + MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) );1.2533 } else {1.2534 - LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );1.2535 - call_func1( sh4_ftrv, R_EAX );1.2536 + LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX );1.2537 + call_func1( sh4_ftrv, REG_EAX );1.2538 }1.2539 }1.2540 sh4_x86.tstate = TSTATE_NONE;1.2541 @@ -2251,15 +2257,15 @@1.2542 FRCHG {:1.2543 COUNT_INST(I_FRCHG);1.2544 check_fpuen();1.2545 - XOR_imm32_sh4r( FPSCR_FR, R_FPSCR );1.2546 + XORL_imms_rbpdisp( FPSCR_FR, R_FPSCR );1.2547 call_func0( sh4_switch_fr_banks );1.2548 sh4_x86.tstate = TSTATE_NONE;1.2549 :}1.2550 FSCHG {:1.2551 COUNT_INST(I_FSCHG);1.2552 check_fpuen();1.2553 - XOR_imm32_sh4r( FPSCR_SZ, R_FPSCR);1.2554 - XOR_imm32_sh4r( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );1.2555 + XORL_imms_rbpdisp( FPSCR_SZ, R_FPSCR);1.2556 + XORL_imms_rbpdisp( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );1.2557 sh4_x86.tstate = TSTATE_NONE;1.2558 sh4_x86.double_size = !sh4_x86.double_size;1.2559 :}1.2560 @@ -2271,8 +2277,8 @@1.2561 SLOTILLEGAL();1.2562 } else {1.2563 check_priv();1.2564 - load_reg( R_EAX, Rm );1.2565 - call_func1( sh4_write_sr, R_EAX );1.2566 + load_reg( REG_EAX, Rm );1.2567 + call_func1( sh4_write_sr, REG_EAX );1.2568 sh4_x86.fpuen_checked = FALSE;1.2569 sh4_x86.tstate = TSTATE_NONE;1.2570 return 2;1.2571 @@ -2280,58 +2286,58 @@1.2572 :}1.2573 LDC Rm, GBR {:1.2574 COUNT_INST(I_LDC);1.2575 - load_reg( R_EAX, Rm );1.2576 - store_spreg( R_EAX, R_GBR );1.2577 + load_reg( REG_EAX, Rm );1.2578 + store_spreg( REG_EAX, R_GBR );1.2579 :}1.2580 LDC Rm, VBR {:1.2581 COUNT_INST(I_LDC);1.2582 check_priv();1.2583 - load_reg( R_EAX, Rm );1.2584 - store_spreg( R_EAX, R_VBR );1.2585 + load_reg( REG_EAX, Rm );1.2586 + store_spreg( REG_EAX, R_VBR );1.2587 sh4_x86.tstate = TSTATE_NONE;1.2588 :}1.2589 LDC Rm, SSR {:1.2590 COUNT_INST(I_LDC);1.2591 check_priv();1.2592 - load_reg( R_EAX, Rm );1.2593 - store_spreg( R_EAX, R_SSR );1.2594 + load_reg( REG_EAX, Rm );1.2595 + store_spreg( REG_EAX, R_SSR );1.2596 sh4_x86.tstate = TSTATE_NONE;1.2597 :}1.2598 LDC Rm, SGR {:1.2599 COUNT_INST(I_LDC);1.2600 check_priv();1.2601 - load_reg( R_EAX, Rm );1.2602 - store_spreg( R_EAX, R_SGR );1.2603 + load_reg( REG_EAX, Rm );1.2604 + store_spreg( REG_EAX, R_SGR );1.2605 sh4_x86.tstate = TSTATE_NONE;1.2606 :}1.2607 LDC Rm, SPC {:1.2608 COUNT_INST(I_LDC);1.2609 check_priv();1.2610 - load_reg( R_EAX, Rm );1.2611 - store_spreg( R_EAX, R_SPC );1.2612 + load_reg( REG_EAX, Rm );1.2613 + store_spreg( REG_EAX, R_SPC );1.2614 sh4_x86.tstate = TSTATE_NONE;1.2615 :}1.2616 LDC Rm, DBR {:1.2617 COUNT_INST(I_LDC);1.2618 check_priv();1.2619 - load_reg( R_EAX, Rm );1.2620 - store_spreg( R_EAX, R_DBR );1.2621 + load_reg( REG_EAX, Rm );1.2622 + store_spreg( REG_EAX, R_DBR );1.2623 sh4_x86.tstate = TSTATE_NONE;1.2624 :}1.2625 LDC Rm, Rn_BANK {:1.2626 COUNT_INST(I_LDC);1.2627 check_priv();1.2628 - load_reg( R_EAX, Rm );1.2629 - store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );1.2630 + load_reg( REG_EAX, Rm );1.2631 + store_spreg( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );1.2632 sh4_x86.tstate = TSTATE_NONE;1.2633 :}1.2634 LDC.L @Rm+, GBR {:1.2635 COUNT_INST(I_LDCM);1.2636 - load_reg( R_EAX, Rm );1.2637 - check_ralign32( R_EAX );1.2638 - MEM_READ_LONG( R_EAX, R_EAX );1.2639 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2640 - store_spreg( R_EAX, R_GBR );1.2641 + load_reg( REG_EAX, Rm );1.2642 + check_ralign32( REG_EAX );1.2643 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2644 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2645 + store_spreg( REG_EAX, R_GBR );1.2646 sh4_x86.tstate = TSTATE_NONE;1.2647 :}1.2648 LDC.L @Rm+, SR {:1.2649 @@ -2340,11 +2346,11 @@1.2650 SLOTILLEGAL();1.2651 } else {1.2652 check_priv();1.2653 - load_reg( R_EAX, Rm );1.2654 - check_ralign32( R_EAX );1.2655 - MEM_READ_LONG( R_EAX, R_EAX );1.2656 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2657 - call_func1( sh4_write_sr, R_EAX );1.2658 + load_reg( REG_EAX, Rm );1.2659 + check_ralign32( REG_EAX );1.2660 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2661 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2662 + call_func1( sh4_write_sr, REG_EAX );1.2663 sh4_x86.fpuen_checked = FALSE;1.2664 sh4_x86.tstate = TSTATE_NONE;1.2665 return 2;1.2666 @@ -2353,138 +2359,138 @@1.2667 LDC.L @Rm+, VBR {:1.2668 COUNT_INST(I_LDCM);1.2669 check_priv();1.2670 - load_reg( R_EAX, Rm );1.2671 - check_ralign32( R_EAX );1.2672 - MEM_READ_LONG( R_EAX, R_EAX );1.2673 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2674 - store_spreg( R_EAX, R_VBR );1.2675 + load_reg( REG_EAX, Rm );1.2676 + check_ralign32( REG_EAX );1.2677 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2678 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2679 + store_spreg( REG_EAX, R_VBR );1.2680 sh4_x86.tstate = TSTATE_NONE;1.2681 :}1.2682 LDC.L @Rm+, SSR {:1.2683 COUNT_INST(I_LDCM);1.2684 check_priv();1.2685 - load_reg( R_EAX, Rm );1.2686 - check_ralign32( R_EAX );1.2687 - MEM_READ_LONG( R_EAX, R_EAX );1.2688 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2689 - store_spreg( R_EAX, R_SSR );1.2690 + load_reg( REG_EAX, Rm );1.2691 + check_ralign32( REG_EAX );1.2692 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2693 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2694 + store_spreg( REG_EAX, R_SSR );1.2695 sh4_x86.tstate = TSTATE_NONE;1.2696 :}1.2697 LDC.L @Rm+, SGR {:1.2698 COUNT_INST(I_LDCM);1.2699 check_priv();1.2700 - load_reg( R_EAX, Rm );1.2701 - check_ralign32( R_EAX );1.2702 - MEM_READ_LONG( R_EAX, R_EAX );1.2703 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2704 - store_spreg( R_EAX, R_SGR );1.2705 + load_reg( REG_EAX, Rm );1.2706 + check_ralign32( REG_EAX );1.2707 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2708 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2709 + store_spreg( REG_EAX, R_SGR );1.2710 sh4_x86.tstate = TSTATE_NONE;1.2711 :}1.2712 LDC.L @Rm+, SPC {:1.2713 COUNT_INST(I_LDCM);1.2714 check_priv();1.2715 - load_reg( R_EAX, Rm );1.2716 - check_ralign32( R_EAX );1.2717 - MEM_READ_LONG( R_EAX, R_EAX );1.2718 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2719 - store_spreg( R_EAX, R_SPC );1.2720 + load_reg( REG_EAX, Rm );1.2721 + check_ralign32( REG_EAX );1.2722 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2723 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2724 + store_spreg( REG_EAX, R_SPC );1.2725 sh4_x86.tstate = TSTATE_NONE;1.2726 :}1.2727 LDC.L @Rm+, DBR {:1.2728 COUNT_INST(I_LDCM);1.2729 check_priv();1.2730 - load_reg( R_EAX, Rm );1.2731 - check_ralign32( R_EAX );1.2732 - MEM_READ_LONG( R_EAX, R_EAX );1.2733 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2734 - store_spreg( R_EAX, R_DBR );1.2735 + load_reg( REG_EAX, Rm );1.2736 + check_ralign32( REG_EAX );1.2737 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2738 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2739 + store_spreg( REG_EAX, R_DBR );1.2740 sh4_x86.tstate = TSTATE_NONE;1.2741 :}1.2742 LDC.L @Rm+, Rn_BANK {:1.2743 COUNT_INST(I_LDCM);1.2744 check_priv();1.2745 - load_reg( R_EAX, Rm );1.2746 - check_ralign32( R_EAX );1.2747 - MEM_READ_LONG( R_EAX, R_EAX );1.2748 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2749 - store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );1.2750 + load_reg( REG_EAX, Rm );1.2751 + check_ralign32( REG_EAX );1.2752 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2753 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2754 + store_spreg( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );1.2755 sh4_x86.tstate = TSTATE_NONE;1.2756 :}1.2757 LDS Rm, FPSCR {:1.2758 COUNT_INST(I_LDSFPSCR);1.2759 check_fpuen();1.2760 - load_reg( R_EAX, Rm );1.2761 - call_func1( sh4_write_fpscr, R_EAX );1.2762 + load_reg( REG_EAX, Rm );1.2763 + call_func1( sh4_write_fpscr, REG_EAX );1.2764 sh4_x86.tstate = TSTATE_NONE;1.2765 return 2;1.2766 :}1.2767 LDS.L @Rm+, FPSCR {:1.2768 COUNT_INST(I_LDSFPSCRM);1.2769 check_fpuen();1.2770 - load_reg( R_EAX, Rm );1.2771 - check_ralign32( R_EAX );1.2772 - MEM_READ_LONG( R_EAX, R_EAX );1.2773 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2774 - call_func1( sh4_write_fpscr, R_EAX );1.2775 + load_reg( REG_EAX, Rm );1.2776 + check_ralign32( REG_EAX );1.2777 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2778 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2779 + call_func1( sh4_write_fpscr, REG_EAX );1.2780 sh4_x86.tstate = TSTATE_NONE;1.2781 return 2;1.2782 :}1.2783 LDS Rm, FPUL {:1.2784 COUNT_INST(I_LDS);1.2785 check_fpuen();1.2786 - load_reg( R_EAX, Rm );1.2787 - store_spreg( R_EAX, R_FPUL );1.2788 + load_reg( REG_EAX, Rm );1.2789 + store_spreg( REG_EAX, R_FPUL );1.2790 :}1.2791 LDS.L @Rm+, FPUL {:1.2792 COUNT_INST(I_LDSM);1.2793 check_fpuen();1.2794 - load_reg( R_EAX, Rm );1.2795 - check_ralign32( R_EAX );1.2796 - MEM_READ_LONG( R_EAX, R_EAX );1.2797 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2798 - store_spreg( R_EAX, R_FPUL );1.2799 + load_reg( REG_EAX, Rm );1.2800 + check_ralign32( REG_EAX );1.2801 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2802 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2803 + store_spreg( REG_EAX, R_FPUL );1.2804 sh4_x86.tstate = TSTATE_NONE;1.2805 :}1.2806 LDS Rm, MACH {:1.2807 COUNT_INST(I_LDS);1.2808 - load_reg( R_EAX, Rm );1.2809 - store_spreg( R_EAX, R_MACH );1.2810 + load_reg( REG_EAX, Rm );1.2811 + store_spreg( REG_EAX, R_MACH );1.2812 :}1.2813 LDS.L @Rm+, MACH {:1.2814 COUNT_INST(I_LDSM);1.2815 - load_reg( R_EAX, Rm );1.2816 - check_ralign32( R_EAX );1.2817 - MEM_READ_LONG( R_EAX, R_EAX );1.2818 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2819 - store_spreg( R_EAX, R_MACH );1.2820 + load_reg( REG_EAX, Rm );1.2821 + check_ralign32( REG_EAX );1.2822 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2823 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2824 + store_spreg( REG_EAX, R_MACH );1.2825 sh4_x86.tstate = TSTATE_NONE;1.2826 :}1.2827 LDS Rm, MACL {:1.2828 COUNT_INST(I_LDS);1.2829 - load_reg( R_EAX, Rm );1.2830 - store_spreg( R_EAX, R_MACL );1.2831 + load_reg( REG_EAX, Rm );1.2832 + store_spreg( REG_EAX, R_MACL );1.2833 :}1.2834 LDS.L @Rm+, MACL {:1.2835 COUNT_INST(I_LDSM);1.2836 - load_reg( R_EAX, Rm );1.2837 - check_ralign32( R_EAX );1.2838 - MEM_READ_LONG( R_EAX, R_EAX );1.2839 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2840 - store_spreg( R_EAX, R_MACL );1.2841 + load_reg( REG_EAX, Rm );1.2842 + check_ralign32( REG_EAX );1.2843 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2844 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2845 + store_spreg( REG_EAX, R_MACL );1.2846 sh4_x86.tstate = TSTATE_NONE;1.2847 :}1.2848 LDS Rm, PR {:1.2849 COUNT_INST(I_LDS);1.2850 - load_reg( R_EAX, Rm );1.2851 - store_spreg( R_EAX, R_PR );1.2852 + load_reg( REG_EAX, Rm );1.2853 + store_spreg( REG_EAX, R_PR );1.2854 :}1.2855 LDS.L @Rm+, PR {:1.2856 COUNT_INST(I_LDSM);1.2857 - load_reg( R_EAX, Rm );1.2858 - check_ralign32( R_EAX );1.2859 - MEM_READ_LONG( R_EAX, R_EAX );1.2860 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.2861 - store_spreg( R_EAX, R_PR );1.2862 + load_reg( REG_EAX, Rm );1.2863 + check_ralign32( REG_EAX );1.2864 + MEM_READ_LONG( REG_EAX, REG_EAX );1.2865 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );1.2866 + store_spreg( REG_EAX, R_PR );1.2867 sh4_x86.tstate = TSTATE_NONE;1.2868 :}1.2869 LDTLB {:1.2870 @@ -2503,8 +2509,8 @@1.2871 :}1.2872 PREF @Rn {:1.2873 COUNT_INST(I_PREF);1.2874 - load_reg( R_EAX, Rn );1.2875 - MEM_PREFETCH( R_EAX );1.2876 + load_reg( REG_EAX, Rn );1.2877 + MEM_PREFETCH( REG_EAX );1.2878 sh4_x86.tstate = TSTATE_NONE;1.2879 :}1.2880 SLEEP {:1.2881 @@ -2519,221 +2525,221 @@1.2882 COUNT_INST(I_STCSR);1.2883 check_priv();1.2884 call_func0(sh4_read_sr);1.2885 - store_reg( R_EAX, Rn );1.2886 + store_reg( REG_EAX, Rn );1.2887 sh4_x86.tstate = TSTATE_NONE;1.2888 :}1.2889 STC GBR, Rn {:1.2890 COUNT_INST(I_STC);1.2891 - load_spreg( R_EAX, R_GBR );1.2892 - store_reg( R_EAX, Rn );1.2893 + load_spreg( REG_EAX, R_GBR );1.2894 + store_reg( REG_EAX, Rn );1.2895 :}1.2896 STC VBR, Rn {:1.2897 COUNT_INST(I_STC);1.2898 check_priv();1.2899 - load_spreg( R_EAX, R_VBR );1.2900 - store_reg( R_EAX, Rn );1.2901 + load_spreg( REG_EAX, R_VBR );1.2902 + store_reg( REG_EAX, Rn );1.2903 sh4_x86.tstate = TSTATE_NONE;1.2904 :}1.2905 STC SSR, Rn {:1.2906 COUNT_INST(I_STC);1.2907 check_priv();1.2908 - load_spreg( R_EAX, R_SSR );1.2909 - store_reg( R_EAX, Rn );1.2910 + load_spreg( REG_EAX, R_SSR );1.2911 + store_reg( REG_EAX, Rn );1.2912 sh4_x86.tstate = TSTATE_NONE;1.2913 :}1.2914 STC SPC, Rn {:1.2915 COUNT_INST(I_STC);1.2916 check_priv();1.2917 - load_spreg( R_EAX, R_SPC );1.2918 - store_reg( R_EAX, Rn );1.2919 + load_spreg( REG_EAX, R_SPC );1.2920 + store_reg( REG_EAX, Rn );1.2921 sh4_x86.tstate = TSTATE_NONE;1.2922 :}1.2923 STC SGR, Rn {:1.2924 COUNT_INST(I_STC);1.2925 check_priv();1.2926 - load_spreg( R_EAX, R_SGR );1.2927 - store_reg( R_EAX, Rn );1.2928 + load_spreg( REG_EAX, R_SGR );1.2929 + store_reg( REG_EAX, Rn );1.2930 sh4_x86.tstate = TSTATE_NONE;1.2931 :}1.2932 STC DBR, Rn {:1.2933 COUNT_INST(I_STC);1.2934 check_priv();1.2935 - load_spreg( R_EAX, R_DBR );1.2936 - store_reg( R_EAX, Rn );1.2937 + load_spreg( REG_EAX, R_DBR );1.2938 + store_reg( REG_EAX, Rn );1.2939 sh4_x86.tstate = TSTATE_NONE;1.2940 :}1.2941 STC Rm_BANK, Rn {:1.2942 COUNT_INST(I_STC);1.2943 check_priv();1.2944 - load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );1.2945 - store_reg( R_EAX, Rn );1.2946 + load_spreg( REG_EAX, REG_OFFSET(r_bank[Rm_BANK]) );1.2947 + store_reg( REG_EAX, Rn );1.2948 sh4_x86.tstate = TSTATE_NONE;1.2949 :}1.2950 STC.L SR, @-Rn {:1.2951 COUNT_INST(I_STCSRM);1.2952 check_priv();1.2953 call_func0( sh4_read_sr );1.2954 - MOV_r32_r32( R_EAX, R_EDX );1.2955 - load_reg( R_EAX, Rn );1.2956 - check_walign32( R_EAX );1.2957 - LEA_r32disp8_r32( R_EAX, -4, R_EAX );1.2958 - MEM_WRITE_LONG( R_EAX, R_EDX );1.2959 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.2960 + MOVL_r32_r32( REG_EAX, REG_EDX );1.2961 + load_reg( REG_EAX, Rn );1.2962 + check_walign32( REG_EAX );1.2963 + LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );1.2964 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.2965 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.2966 sh4_x86.tstate = TSTATE_NONE;1.2967 :}1.2968 STC.L VBR, @-Rn {:1.2969 COUNT_INST(I_STCM);1.2970 check_priv();1.2971 - load_reg( R_EAX, Rn );1.2972 - check_walign32( R_EAX );1.2973 - ADD_imm8s_r32( -4, R_EAX );1.2974 - load_spreg( R_EDX, R_VBR );1.2975 - MEM_WRITE_LONG( R_EAX, R_EDX );1.2976 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.2977 + load_reg( REG_EAX, Rn );1.2978 + check_walign32( REG_EAX );1.2979 + ADDL_imms_r32( -4, REG_EAX );1.2980 + load_spreg( REG_EDX, R_VBR );1.2981 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.2982 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.2983 sh4_x86.tstate = TSTATE_NONE;1.2984 :}1.2985 STC.L SSR, @-Rn {:1.2986 COUNT_INST(I_STCM);1.2987 check_priv();1.2988 - load_reg( R_EAX, Rn );1.2989 - check_walign32( R_EAX );1.2990 - ADD_imm8s_r32( -4, R_EAX );1.2991 - load_spreg( R_EDX, R_SSR );1.2992 - MEM_WRITE_LONG( R_EAX, R_EDX );1.2993 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.2994 + load_reg( REG_EAX, Rn );1.2995 + check_walign32( REG_EAX );1.2996 + ADDL_imms_r32( -4, REG_EAX );1.2997 + load_spreg( REG_EDX, R_SSR );1.2998 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.2999 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.3000 sh4_x86.tstate = TSTATE_NONE;1.3001 :}1.3002 STC.L SPC, @-Rn {:1.3003 COUNT_INST(I_STCM);1.3004 check_priv();1.3005 - load_reg( R_EAX, Rn );1.3006 - check_walign32( R_EAX );1.3007 - ADD_imm8s_r32( -4, R_EAX );1.3008 - load_spreg( R_EDX, R_SPC );1.3009 - MEM_WRITE_LONG( R_EAX, R_EDX );1.3010 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.3011 + load_reg( REG_EAX, Rn );1.3012 + check_walign32( REG_EAX );1.3013 + ADDL_imms_r32( -4, REG_EAX );1.3014 + load_spreg( REG_EDX, R_SPC );1.3015 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.3016 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.3017 sh4_x86.tstate = TSTATE_NONE;1.3018 :}1.3019 STC.L SGR, @-Rn {:1.3020 COUNT_INST(I_STCM);1.3021 check_priv();1.3022 - load_reg( R_EAX, Rn );1.3023 - check_walign32( R_EAX );1.3024 - ADD_imm8s_r32( -4, R_EAX );1.3025 - load_spreg( R_EDX, R_SGR );1.3026 - MEM_WRITE_LONG( R_EAX, R_EDX );1.3027 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.3028 + load_reg( REG_EAX, Rn );1.3029 + check_walign32( REG_EAX );1.3030 + ADDL_imms_r32( -4, REG_EAX );1.3031 + load_spreg( REG_EDX, R_SGR );1.3032 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.3033 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.3034 sh4_x86.tstate = TSTATE_NONE;1.3035 :}1.3036 STC.L DBR, @-Rn {:1.3037 COUNT_INST(I_STCM);1.3038 check_priv();1.3039 - load_reg( R_EAX, Rn );1.3040 - check_walign32( R_EAX );1.3041 - ADD_imm8s_r32( -4, R_EAX );1.3042 - load_spreg( R_EDX, R_DBR );1.3043 - MEM_WRITE_LONG( R_EAX, R_EDX );1.3044 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.3045 + load_reg( REG_EAX, Rn );1.3046 + check_walign32( REG_EAX );1.3047 + ADDL_imms_r32( -4, REG_EAX );1.3048 + load_spreg( REG_EDX, R_DBR );1.3049 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.3050 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.3051 sh4_x86.tstate = TSTATE_NONE;1.3052 :}1.3053 STC.L Rm_BANK, @-Rn {:1.3054 COUNT_INST(I_STCM);1.3055 check_priv();1.3056 - load_reg( R_EAX, Rn );1.3057 - check_walign32( R_EAX );1.3058 - ADD_imm8s_r32( -4, R_EAX );1.3059 - load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );1.3060 - MEM_WRITE_LONG( R_EAX, R_EDX );1.3061 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.3062 + load_reg( REG_EAX, Rn );1.3063 + check_walign32( REG_EAX );1.3064 + ADDL_imms_r32( -4, REG_EAX );1.3065 + load_spreg( REG_EDX, REG_OFFSET(r_bank[Rm_BANK]) );1.3066 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.3067 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.3068 sh4_x86.tstate = TSTATE_NONE;1.3069 :}1.3070 STC.L GBR, @-Rn {:1.3071 COUNT_INST(I_STCM);1.3072 - load_reg( R_EAX, Rn );1.3073 - check_walign32( R_EAX );1.3074 - ADD_imm8s_r32( -4, R_EAX );1.3075 - load_spreg( R_EDX, R_GBR );1.3076 - MEM_WRITE_LONG( R_EAX, R_EDX );1.3077 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.3078 + load_reg( REG_EAX, Rn );1.3079 + check_walign32( REG_EAX );1.3080 + ADDL_imms_r32( -4, REG_EAX );1.3081 + load_spreg( REG_EDX, R_GBR );1.3082 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.3083 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.3084 sh4_x86.tstate = TSTATE_NONE;1.3085 :}1.3086 STS FPSCR, Rn {:1.3087 COUNT_INST(I_STSFPSCR);1.3088 check_fpuen();1.3089 - load_spreg( R_EAX, R_FPSCR );1.3090 - store_reg( R_EAX, Rn );1.3091 + load_spreg( REG_EAX, R_FPSCR );1.3092 + store_reg( REG_EAX, Rn );1.3093 :}1.3094 STS.L FPSCR, @-Rn {:1.3095 COUNT_INST(I_STSFPSCRM);1.3096 check_fpuen();1.3097 - load_reg( R_EAX, Rn );1.3098 - check_walign32( R_EAX );1.3099 - ADD_imm8s_r32( -4, R_EAX );1.3100 - load_spreg( R_EDX, R_FPSCR );1.3101 - MEM_WRITE_LONG( R_EAX, R_EDX );1.3102 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.3103 + load_reg( REG_EAX, Rn );1.3104 + check_walign32( REG_EAX );1.3105 + ADDL_imms_r32( -4, REG_EAX );1.3106 + load_spreg( REG_EDX, R_FPSCR );1.3107 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.3108 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.3109 sh4_x86.tstate = TSTATE_NONE;1.3110 :}1.3111 STS FPUL, Rn {:1.3112 COUNT_INST(I_STS);1.3113 check_fpuen();1.3114 - load_spreg( R_EAX, R_FPUL );1.3115 - store_reg( R_EAX, Rn );1.3116 + load_spreg( REG_EAX, R_FPUL );1.3117 + store_reg( REG_EAX, Rn );1.3118 :}1.3119 STS.L FPUL, @-Rn {:1.3120 COUNT_INST(I_STSM);1.3121 check_fpuen();1.3122 - load_reg( R_EAX, Rn );1.3123 - check_walign32( R_EAX );1.3124 - ADD_imm8s_r32( -4, R_EAX );1.3125 - load_spreg( R_EDX, R_FPUL );1.3126 - MEM_WRITE_LONG( R_EAX, R_EDX );1.3127 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.3128 + load_reg( REG_EAX, Rn );1.3129 + check_walign32( REG_EAX );1.3130 + ADDL_imms_r32( -4, REG_EAX );1.3131 + load_spreg( REG_EDX, R_FPUL );1.3132 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.3133 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.3134 sh4_x86.tstate = TSTATE_NONE;1.3135 :}1.3136 STS MACH, Rn {:1.3137 COUNT_INST(I_STS);1.3138 - load_spreg( R_EAX, R_MACH );1.3139 - store_reg( R_EAX, Rn );1.3140 + load_spreg( REG_EAX, R_MACH );1.3141 + store_reg( REG_EAX, Rn );1.3142 :}1.3143 STS.L MACH, @-Rn {:1.3144 COUNT_INST(I_STSM);1.3145 - load_reg( R_EAX, Rn );1.3146 - check_walign32( R_EAX );1.3147 - ADD_imm8s_r32( -4, R_EAX );1.3148 - load_spreg( R_EDX, R_MACH );1.3149 - MEM_WRITE_LONG( R_EAX, R_EDX );1.3150 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.3151 + load_reg( REG_EAX, Rn );1.3152 + check_walign32( REG_EAX );1.3153 + ADDL_imms_r32( -4, REG_EAX );1.3154 + load_spreg( REG_EDX, R_MACH );1.3155 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.3156 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.3157 sh4_x86.tstate = TSTATE_NONE;1.3158 :}1.3159 STS MACL, Rn {:1.3160 COUNT_INST(I_STS);1.3161 - load_spreg( R_EAX, R_MACL );1.3162 - store_reg( R_EAX, Rn );1.3163 + load_spreg( REG_EAX, R_MACL );1.3164 + store_reg( REG_EAX, Rn );1.3165 :}1.3166 STS.L MACL, @-Rn {:1.3167 COUNT_INST(I_STSM);1.3168 - load_reg( R_EAX, Rn );1.3169 - check_walign32( R_EAX );1.3170 - ADD_imm8s_r32( -4, R_EAX );1.3171 - load_spreg( R_EDX, R_MACL );1.3172 - MEM_WRITE_LONG( R_EAX, R_EDX );1.3173 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.3174 + load_reg( REG_EAX, Rn );1.3175 + check_walign32( REG_EAX );1.3176 + ADDL_imms_r32( -4, REG_EAX );1.3177 + load_spreg( REG_EDX, R_MACL );1.3178 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.3179 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.3180 sh4_x86.tstate = TSTATE_NONE;1.3181 :}1.3182 STS PR, Rn {:1.3183 COUNT_INST(I_STS);1.3184 - load_spreg( R_EAX, R_PR );1.3185 - store_reg( R_EAX, Rn );1.3186 + load_spreg( REG_EAX, R_PR );1.3187 + store_reg( REG_EAX, Rn );1.3188 :}1.3189 STS.L PR, @-Rn {:1.3190 COUNT_INST(I_STSM);1.3191 - load_reg( R_EAX, Rn );1.3192 - check_walign32( R_EAX );1.3193 - ADD_imm8s_r32( -4, R_EAX );1.3194 - load_spreg( R_EDX, R_PR );1.3195 - MEM_WRITE_LONG( R_EAX, R_EDX );1.3196 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.3197 + load_reg( REG_EAX, Rn );1.3198 + check_walign32( REG_EAX );1.3199 + ADDL_imms_r32( -4, REG_EAX );1.3200 + load_spreg( REG_EDX, R_PR );1.3201 + MEM_WRITE_LONG( REG_EAX, REG_EDX );1.3202 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );1.3203 sh4_x86.tstate = TSTATE_NONE;1.3204 :}
.