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lxdream 0.9.1
released Jun 29
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filename src/xlat/x86/x86op.h
changeset 991:60c7fab9c880
next995:eb9d43e8aa08
author nkeynes
date Wed Mar 04 23:12:21 2009 +0000 (13 years ago)
permissions -rw-r--r--
last change Move xltcache to xlat/ src directory
Commit new and improved x86 opcode file - cleaned up and added support for amd64 extended registers
file annotate diff log raw
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/xlat/x86/x86op.h Wed Mar 04 23:12:21 2009 +0000
1.3 @@ -0,0 +1,768 @@
1.4 +/**
1.5 + * $Id$
1.6 + *
1.7 + * x86/x86-64 Instruction generation macros
1.8 + *
1.9 + * Copyright (c) 2009 Nathan Keynes.
1.10 + *
1.11 + * This program is free software; you can redistribute it and/or modify
1.12 + * it under the terms of the GNU General Public License as published by
1.13 + * the Free Software Foundation; either version 2 of the License, or
1.14 + * (at your option) any later version.
1.15 + *
1.16 + * This program is distributed in the hope that it will be useful,
1.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.19 + * GNU General Public License for more details.
1.20 + */
1.21 +#include <stdint.h>
1.22 +#include <assert.h>
1.23 +
1.24 +/******************************** Constants *****************************/
1.25 +
1.26 +#define REG_NONE -1
1.27 +
1.28 +/* 64-bit general-purpose regs */
1.29 +#define REG_RAX 0
1.30 +#define REG_RCX 1
1.31 +#define REG_RDX 2
1.32 +#define REG_RBX 3
1.33 +#define REG_RSP 4
1.34 +#define REG_RBP 5
1.35 +#define REG_RSI 6
1.36 +#define REG_RDI 7
1.37 +#define REG_R8 8
1.38 +#define REG_R9 9
1.39 +#define REG_R10 10
1.40 +#define REG_R11 11
1.41 +#define REG_R12 12
1.42 +#define REG_R13 13
1.43 +#define REG_R14 14
1.44 +#define REG_R15 15
1.45 +
1.46 +/* 32-bit general-purpose regs */
1.47 +#define REG_EAX 0
1.48 +#define REG_ECX 1
1.49 +#define REG_EDX 2
1.50 +#define REG_EBX 3
1.51 +#define REG_ESP 4
1.52 +#define REG_EBP 5
1.53 +#define REG_ESI 6
1.54 +#define REG_EDI 7
1.55 +#define REG_R8D 8
1.56 +#define REG_R9D 9
1.57 +#define REG_R10D 10
1.58 +#define REG_R11D 11
1.59 +#define REG_R12D 12
1.60 +#define REG_R13D 13
1.61 +#define REG_R14D 14
1.62 +#define REG_R15D 15
1.63 +
1.64 +/* 8-bit general-purpose regs (no-rex prefix) */
1.65 +#define REG_AL 0
1.66 +#define REG_CL 1
1.67 +#define REG_DL 2
1.68 +#define REG_BL 3
1.69 +#define REG_AH 4
1.70 +#define REG_CH 5
1.71 +#define REG_DH 6
1.72 +#define REG_BH 7
1.73 +
1.74 +/* 8-bit general-purpose regs (rex-prefix) */
1.75 +#define REG_SPL 4
1.76 +#define REG_BPL 5
1.77 +#define REG_SIL 6
1.78 +#define REG_DIL 7
1.79 +#define REG_R8L 8
1.80 +#define REG_R9L 9
1.81 +#define REG_R10L 10
1.82 +#define REG_R11L 11
1.83 +#define REG_R12L 12
1.84 +#define REG_R13L 13
1.85 +#define REG_R14L 14
1.86 +#define REG_R15L 15
1.87 +
1.88 +/* Condition flag variants */
1.89 +#define X86_COND_O 0x00 /* OF=1 */
1.90 +#define X86_COND_NO 0x01 /* OF=0 */
1.91 +#define X86_COND_B 0x02 /* CF=1 */
1.92 +#define X86_COND_C 0x02 /* CF=1 */
1.93 +#define X86_CONF_NAE 0x02 /* CF=1 */
1.94 +#define X86_COND_AE 0x03 /* CF=0 */
1.95 +#define X86_COND_NB 0x03 /* CF=0 */
1.96 +#define X86_COND_NC 0x03 /* CF=0 */
1.97 +#define X86_COND_E 0x04 /* ZF=1 */
1.98 +#define X86_COND_Z 0x04 /* ZF=1 */
1.99 +#define X86_COND_NE 0x05 /* ZF=0 */
1.100 +#define X86_COND_NZ 0x05 /* ZF=0 */
1.101 +#define X86_COND_BE 0x06 /* CF=1 || ZF=1 */
1.102 +#define X86_COND_NA 0x06 /* CF=1 || ZF=1 */
1.103 +#define X86_COND_A 0x07 /* CF=0 && ZF=0 */
1.104 +#define X86_COND_NBE 0x07 /* CF=0 && ZF=0 */
1.105 +#define X86_COND_S 0x08 /* SF=1 */
1.106 +#define X86_COND_NS 0x09 /* SF=0 */
1.107 +#define X86_COND_P 0x0A /* PF=1 */
1.108 +#define X86_COND_PE 0x0A /* PF=1 */
1.109 +#define X86_COND_NP 0x0B /* PF=0 */
1.110 +#define X86_COND_PO 0x0B /* PF=0 */
1.111 +#define X86_COND_L 0x0C /* SF!=OF */
1.112 +#define X86_COND_NGE 0x0C /* SF!=OF */
1.113 +#define X86_COND_GE 0x0D /* SF=OF */
1.114 +#define X86_COND_NL 0x0D /* SF=OF */
1.115 +#define X86_COND_LE 0x0E /* ZF=1 || SF!=OF */
1.116 +#define X86_COND_NG 0x0E /* ZF=1 || SF!=OF */
1.117 +#define X86_COND_G 0x0F /* ZF=0 && SF=OF */
1.118 +#define X86_COND_NLE 0x0F /* ZF=0 && SF=OF */
1.119 +
1.120 +/* SSE floating pointer comparison variants */
1.121 +#define SSE_CMP_EQ 0x00
1.122 +#define SSE_CMP_LT 0x01
1.123 +#define SSE_CMP_LE 0x02
1.124 +#define SSE_CMP_UNORD 0x03
1.125 +#define SSE_CMP_NE 0x04
1.126 +#define SSE_CMP_NLT 0x05
1.127 +#define SSE_CMP_NLE 0x06
1.128 +#define SSE_CMP_ORD 0x07
1.129 +
1.130 +/************************** Internal definitions ***************************/
1.131 +#define PREF_REXB 0x41
1.132 +#define PREF_REXX 0x42
1.133 +#define PREF_REXR 0x44
1.134 +#define PREF_REXW 0x48
1.135 +
1.136 +extern unsigned char *xlat_output;
1.137 +
1.138 +#define OP(x) *xlat_output++ = (x)
1.139 +#define OP16(x) *((uint16_t *)xlat_output) = (x); xlat_output+=2
1.140 +#define OP32(x) *((uint32_t *)xlat_output) = (x); xlat_output+=4
1.141 +#define OP64(x) *((uint64_t *)xlat_output) = (x); xlat_output+=8
1.142 +#define OPPTR(x) *((void **)xlat_output) = ((void *)x); xlat_output+=(sizeof(void*))
1.143 +
1.144 +/* Primary opcode emitter, eg OPCODE(0x0FBE) for MOVSX */
1.145 +#define OPCODE(x) if( (x) > 0xFFFF ) { OP(x>>16); OP((x>>8)&0xFF); OP(x&0xFF); } else if( (x) > 0xFF ) { OP(x>>8); OP(x&0xFF); } else { OP(x); }
1.146 +
1.147 +/* Test if immediate value is representable as a signed 8-bit integer */
1.148 +#define IS_INT8(imm) ((imm) >= INT8_MIN && (imm) <= INT8_MAX)
1.149 +
1.150 +/**
1.151 + * Encode opcode+reg with no mod/rm (eg MOV imm64, r32)
1.152 + */
1.153 +static void x86_encode_opcodereg( int rexw, uint32_t opcode, int reg )
1.154 +{
1.155 + int rex = rexw;
1.156 + reg &= 0x0F;
1.157 + if( reg >= 8 ) {
1.158 + rex |= PREF_REXB;
1.159 + reg -= 8;
1.160 + }
1.161 + if( rex != 0 ) {
1.162 + OP(rex);
1.163 + }
1.164 + OPCODE(opcode + reg);
1.165 +}
1.166 +
1.167 +/**
1.168 + * Encode opcode with mod/rm reg-reg operation.
1.169 + * @param opcode primary instruction opcode
1.170 + * @param rr reg field
1.171 + * @param rb r/m field
1.172 + */
1.173 +static int x86_encode_reg_rm( int rexw, uint32_t opcode, int rr, int rb )
1.174 +{
1.175 + int rex = rexw;
1.176 + rr &= 0x0F;
1.177 + rb &= 0x0F;
1.178 + if( rr >= 8 ) {
1.179 + rex |= PREF_REXR;
1.180 + rr -= 8;
1.181 + }
1.182 + if( rb >= 8 ) {
1.183 + rex |= PREF_REXB;
1.184 + rb -= 8;
1.185 + }
1.186 + if( rex != 0 ) {
1.187 + OP(rex);
1.188 + }
1.189 + OPCODE(opcode);
1.190 + OP(0xC0|(rr<<3)|rb);
1.191 +}
1.192 +
1.193 +/**
1.194 + * Encode opcode + 32-bit mod/rm memory address. (RIP-relative not supported here)
1.195 + * @param rexw REX.W prefix is required, otherwise 0
1.196 + * @param rr Reg-field register (required).
1.197 + * @param rb Base (unscaled) register, or -1 for no base register.
1.198 + * @param rx Index (scaled) register, or -1 for no index register
1.199 + * @param ss Scale shift (0..3) applied to index register (ignored if no index register)
1.200 + * @param disp32 Signed displacement (0 for none)
1.201 + */
1.202 +static void x86_encode_modrm( int rexw, uint32_t opcode, int rr, int rb, int rx, int ss, int32_t disp32 )
1.203 +{
1.204 + /* Construct the rex prefix where necessary */
1.205 + int rex = rexw;
1.206 + rr &= 0x0F;
1.207 + if( rr >= 8 ) {
1.208 + rex |= PREF_REXR;
1.209 + rr -= 8;
1.210 + }
1.211 + if( rb != -1 ) {
1.212 + rb &= 0x0F;
1.213 + if( rb >= 8 ) {
1.214 + rex |= PREF_REXB;
1.215 + rb -= 8;
1.216 + }
1.217 + }
1.218 + if( rx != -1 ) {
1.219 + rx &= 0x0F;
1.220 + if( rx >= 8 ) {
1.221 + rex |= PREF_REXX;
1.222 + rx -= 8;
1.223 + }
1.224 + }
1.225 +
1.226 + if( rex != 0 ) {
1.227 + OP(rex);
1.228 + }
1.229 + OPCODE(opcode);
1.230 +
1.231 + if( rx == -1 ) {
1.232 + if( rb == -1 ) {
1.233 + /* [disp32] displacement only - use SIB form for 64-bit mode safety */
1.234 + OP(0x04|(rr<<3));
1.235 + OP(0x25);
1.236 + OP32(disp32);
1.237 + } else if( rb == REG_ESP ) { /* [%esp + disp32] - SIB is mandatory for %esp/%r12 encodings */
1.238 + if( disp32 == 0 ) {
1.239 + OP(0x04|(rr<<3));
1.240 + OP(0x24);
1.241 + } else if( IS_INT8(disp32) ) {
1.242 + OP(0x44|(rr<<3));
1.243 + OP(0x24);
1.244 + OP((int8_t)disp32);
1.245 + } else {
1.246 + OP(0x84|(rr<<3));
1.247 + OP(0x24);
1.248 + OP32(disp32);
1.249 + }
1.250 + } else {
1.251 + if( disp32 == 0 && rb != REG_EBP ) { /* [%ebp] is encoded as [%ebp+0] */
1.252 + OP((rr<<3)|rb);
1.253 + } else if( IS_INT8(disp32) ) {
1.254 + OP(0x40|(rr<<3)|rb);
1.255 + OP((int8_t)disp32);
1.256 + } else {
1.257 + OP(0x80|(rr<<3)|rb);
1.258 + OP32(disp32);
1.259 + }
1.260 + }
1.261 + } else { /* We have a scaled index. Goody */
1.262 + assert( ((rx != REG_ESP) || (rex&PREF_REXX)) && "Bug: attempt to index through %esp" ); /* Indexing by %esp is impossible */
1.263 + if( rb == -1 ) { /* [disp32 + rx << ss] */
1.264 + OP(0x04|(rr<<3));
1.265 + OP(0x05|(ss<<6)|(rx<<3));
1.266 + OP32(disp32);
1.267 + } else if( disp32 == 0 && rb != REG_EBP ) { /* [rb + rx << ss]. (Again, %ebp needs to be %ebp+0) */
1.268 + OP(0x04|(rr<<3));
1.269 + OP((ss<<6)|(rx<<3)|rb);
1.270 + } else if( IS_INT8(disp32) ) {
1.271 + OP(0x44|(rr<<3));
1.272 + OP((ss<<6)|(rx<<3)|rb);
1.273 + OP((int8_t)disp32);
1.274 + } else {
1.275 + OP(0x84|(rr<<3));
1.276 + OP((ss<<6)|(rx<<3)|rb);
1.277 + OP32(disp32);
1.278 + }
1.279 + }
1.280 +}
1.281 +
1.282 +/**
1.283 + * Encode opcode + RIP-relative mod/rm (64-bit mode only)
1.284 + * @param rexw PREF_REXW or 0
1.285 + * @param opcode primary instruction opcode
1.286 + * @param rr mod/rm reg field
1.287 + * @param disp32 RIP-relative displacement
1.288 + */
1.289 +static void x86_encode_modrm_rip(int rexw, uint32_t opcode, int rr, int32_t disp32)
1.290 +{
1.291 + int rex = rexw;
1.292 + rr &= 0x0F;
1.293 + if( rr >= 8 ) {
1.294 + rex |= PREF_REXR;
1.295 + rr -= 8;
1.296 + }
1.297 + if( rex != 0 ) {
1.298 + OP(rex);
1.299 + }
1.300 + OPCODE(opcode);
1.301 + OP(0x05|(rr<<3));
1.302 + OP32(disp32);
1.303 +}
1.304 +
1.305 +/* 32/64-bit op emitters. 64-bit versions include a rex.w prefix. Note that any
1.306 + * other prefixes (mandatory or otherwise) need to be emitted prior to these
1.307 + * functions
1.308 + */
1.309 +#define x86_encode_opcode64(opcode,reg) x86_encode_opcodereg(PREF_REXW, opcode,reg)
1.310 +#define x86_encode_opcode32(opcode,reg) x86_encode_opcodereg(0,opcode,reg)
1.311 +#define x86_encode_r32_rm32(opcode,rr,rb) x86_encode_reg_rm(0,opcode,rr,rb)
1.312 +#define x86_encode_r64_rm64(opcode,rr,rb) x86_encode_reg_rm(PREF_REXW,opcode,rr,rb)
1.313 +#define x86_encode_r32_mem32(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(0,opcode,rr,rb,rx,ss,disp32)
1.314 +#define x86_encode_r64_mem64(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,rb,rx,ss,disp32)
1.315 +#define x86_encode_rptr_memptr(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm( (sizeof(void *)==8) ? PREF_REXW : 0,opcode,rr,rb,rx,ss,disp32)
1.316 +#define x86_encode_r32_mem32disp32(opcode,rr,rb,disp32) x86_encode_modrm(0,opcode,rr,rb,-1,0,disp32)
1.317 +#define x86_encode_r64_mem64disp64(opcode,rr,rb,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,rb,-1,0,disp32)
1.318 +#define x86_encode_r32_ripdisp32(opcode,rr,disp32) x86_encode_modrm_rip(0,opcode,rr,disp32)
1.319 +#define x86_encode_r64_ripdisp64(opcode,rr,disp32) x86_encode_modrm_rip(PREF_REXW,opcode,rr,disp32)
1.320 +
1.321 +/* Convenience versions for the common rbp/rsp relative displacements */
1.322 +#define x86_encode_r32_rbpdisp32(opcode,rr,disp32) x86_encode_modrm(0,opcode,rr,REG_RBP,-1,0,disp32)
1.323 +#define x86_encode_r64_rbpdisp64(opcode,rr,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,REG_RBP,-1,0,disp32)
1.324 +#define x86_encode_r32_rspdisp32(opcode,rr,disp32) x86_encode_modrm(0,opcode,rr,REG_RSP,-1,0,disp32)
1.325 +#define x86_encode_r64_rspdisp64(opcode,rr,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,REG_RSP,-1,0,disp32)
1.326 +
1.327 +/* Immediate-selection variants (for instructions with imm8s/imm32 variants) */
1.328 +#define x86_encode_imms_rm32(opcode8,opcode32,reg,imm,rb) \
1.329 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r32_rm32(opcode8,reg,rb); OP((int8_t)imm); \
1.330 + } else { x86_encode_r32_rm32(opcode32,reg,rb); OP32(imm); }
1.331 +#define x86_encode_imms_rm64(opcode8,opcode32,reg,imm,rb) \
1.332 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r64_rm64(opcode8,reg,rb); OP((int8_t)imm); \
1.333 + } else { x86_encode_r64_rm64(opcode32,reg,rb); OP32(imm); }
1.334 +#define x86_encode_imms_rbpdisp32(opcode8,opcode32,reg,imm,disp) \
1.335 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r32_rbpdisp32(opcode8,reg,disp); OP((int8_t)imm); \
1.336 + } else { x86_encode_r32_rbpdisp32(opcode32,reg,disp); OP32(imm); }
1.337 +#define x86_encode_imms_r32disp32(opcode8,opcode32,reg,imm,rb,disp) \
1.338 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r32_mem32disp32(opcode8,reg,rb,disp); OP((int8_t)imm); \
1.339 + } else { x86_encode_r32_mem32disp32(opcode32,reg,rb,disp); OP32(imm); }
1.340 +#define x86_encode_imms_rbpdisp64(opcode8,opcode32,reg,imm,disp) \
1.341 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r64_rbpdisp64(opcode8,reg,disp); OP((int8_t)imm); \
1.342 + } else { x86_encode_r64_rbpdisp64(opcode32,reg,disp); OP32(imm); }
1.343 +
1.344 +/*************************** Instruction definitions ***********************/
1.345 +/* Note this does not try to be an exhaustive definition of the instruction -
1.346 + * it generally only has the forms that we actually need here.
1.347 + */
1.348 +/* Core Integer instructions */
1.349 +#define ADCB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 2, r1); OP(imm)
1.350 +#define ADCB_r8_r8(r1,r2) x86_encode_r32_rm32(0x10, r1, r2)
1.351 +#define ADCL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 2, imm, r1)
1.352 +#define ADCL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 2, imm, disp)
1.353 +#define ADCL_r32_r32(r1,r2) x86_encode_r32_rm32(0x11, r1, r2)
1.354 +#define ADCL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x11, r1, disp)
1.355 +#define ADCL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x13, r1, disp)
1.356 +#define ADCQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 2, imm, r1)
1.357 +#define ADCQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x11, r1, r2)
1.358 +
1.359 +#define ADDB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 0, r1); OP(imm)
1.360 +#define ADDB_r8_r8(r1,r2) x86_encode_r32_rm32(0x00, r1, r2)
1.361 +#define ADDL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 0, imm, r1)
1.362 +#define ADDL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83, 0x81, 0, imm, rb, d)
1.363 +#define ADDL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 0, imm, disp)
1.364 +#define ADDL_r32_r32(r1,r2) x86_encode_r32_rm32(0x01, r1, r2)
1.365 +#define ADDL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x01, r1, disp)
1.366 +#define ADDL_r32_r32disp(r1,r2,dsp) x86_encode_r32_mem32disp32(0x01, r1, r2, dsp)
1.367 +#define ADDL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x03, r1, disp)
1.368 +#define ADDQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 0, imm, r1)
1.369 +#define ADDQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x01, r1, r2)
1.370 +
1.371 +#define ANDB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 4, r1); OP(imm)
1.372 +#define ANDB_r8_r8(r1,r2) x86_encode_r32_rm32(0x20, r1, r2)
1.373 +#define ANDL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 4, imm, r1)
1.374 +#define ANDL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,4,imm,disp)
1.375 +#define ANDL_r32_r32(r1,r2) x86_encode_r32_rm32(0x21, r1, r2)
1.376 +#define ANDL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x21, r1, disp)
1.377 +#define ANDL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x23, r1, disp)
1.378 +#define ANDQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x21, r1, r2)
1.379 +#define ANDQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 4, imm, r1)
1.380 +
1.381 +#define CLC() OP(0xF8)
1.382 +#define CLD() OP(0xFC)
1.383 +#define CMC() OP(0xF5)
1.384 +
1.385 +#define CMOVCCL_cc_r32_r32(cc,r1,r2) x86_encode_r32_rm32(0x0F40+(cc), r2, r1)
1.386 +#define CMOVCCL_cc_rbpdisp_r32(cc,d,r1) x86_encode_r32_rbpdisp32(0x0F40+(cc), r1, d)
1.387 +
1.388 +#define CMPB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 7, r1); OP(imm)
1.389 +#define CMPB_imms_rbpdisp(imm,disp) x86_encode_r32_rbpdisp32(0x80, 7, disp); OP(imm)
1.390 +#define CMPB_r8_r8(r1,r2) x86_encode_r32_rm32(0x38, r1, r2)
1.391 +#define CMPL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 7, imm, r1)
1.392 +#define CMPL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 7, imm, disp)
1.393 +#define CMPL_r32_r32(r1,r2) x86_encode_r32_rm32(0x39, r1, r2)
1.394 +#define CMPL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x39, r1, disp)
1.395 +#define CMPL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x3B, r1, disp)
1.396 +#define CMPQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 7, imm, r1)
1.397 +#define CMPQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x39, r1, r2)
1.398 +
1.399 +#define IDIVL_r32(r1) x86_encode_r32_rm32(0xF7, 7, r1)
1.400 +#define IDIVL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7, 7, disp)
1.401 +#define IDIVQ_r64(r1) x86_encode_r64_rm64(0xF7, 7, r1)
1.402 +
1.403 +#define IMULL_imms_r32(imm,r1) x86_encode_imms_rm32(0x6B,0x69, r1, imm, r1)
1.404 +#define IMULL_r32(r1) x86_encode_r32_rm32(0xF7, 5, r1)
1.405 +#define IMULL_r32_r32(r1,r2) x86_encode_r32_rm32(0x0FAF, r2, r1)
1.406 +#define IMULL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7, 5, disp)
1.407 +#define IMULL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0FAF, r1, disp)
1.408 +#define IMULL_rspdisp(disp) x86_encode_r32_rspdisp32(0xF7, 5, disp)
1.409 +#define IMULL_rspdisp_r32(disp,r1) x86_encode_r32_rspdisp32(0x0FAF, r1, disp)
1.410 +#define IMULQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x6B,0x69, r1, imm, r1)
1.411 +#define IMULQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x0FAF, r2, r1)
1.412 +
1.413 +#define LEAL_r32disp_r32(r1,disp,r2) x86_encode_r32_mem32(0x8D, r2, r1, -1, 0, disp)
1.414 +#define LEAL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x8D, r1, disp)
1.415 +#define LEAL_sib_r32(ss,ii,bb,d,r1) x86_encode_r32_mem32(0x8D, r1, bb, ii, ss, d)
1.416 +#define LEAQ_r64disp_r64(r1,disp,r2) x86_encode_r64_mem64(0x8D, r2, r1, -1, 0, disp)
1.417 +#define LEAQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp64(0x8D, r1, disp)
1.418 +#define LEAP_rptrdisp_rptr(r1,d,r2) x86_encode_rptr_memptr(0x8D, r2, r1, -1, 0, disp)
1.419 +#define LEAP_rbpdisp_rptr(disp,r1) x86_encode_rptr_memptr(0x8D, r1, REG_RBP, -1, 0, disp)
1.420 +#define LEAP_sib_rptr(ss,ii,bb,d,r1) x86_encode_rptr_memptr(0x8D, r1, bb, ii, ss, d)
1.421 +
1.422 +#define MOVB_r8_r8(r1,r2) x86_encode_r32_rm32(0x88, r1, r2)
1.423 +#define MOVL_imm32_r32(i32,r1) x86_encode_opcode32(0xB8, r1); OP32(i32)
1.424 +#define MOVL_imm32_rbpdisp(i,disp) x86_encode_r32_rbpdisp32(0xC7,0,disp); OP32(i)
1.425 +#define MOVL_imm32_rspdisp(i,disp) x86_encode_r32_rspdisp32(0xC7,0,disp); OP32(i)
1.426 +#define MOVL_moffptr_eax(p) OP(0xA1); OPPTR(p)
1.427 +#define MOVL_r32_r32(r1,r2) x86_encode_r32_rm32(0x89, r1, r2)
1.428 +#define MOVL_r32_r32disp(r1,r2,dsp) x86_encode_r32_mem32disp32(0x89, r1, r2, dsp)
1.429 +#define MOVL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x89, r1, disp)
1.430 +#define MOVL_r32_rspdisp(r1,disp) x86_encode_r32_rspdisp32(0x89, r1, disp)
1.431 +#define MOVL_r32_sib(r1,ss,ii,bb,d) x86_encode_r32_mem32(0x89, r1, bb, ii, ss, d)
1.432 +#define MOVL_r32disp_r32(r1,dsp,r2) x86_encode_r32_mem32disp32(0x8B, r2, r1, dsp)
1.433 +#define MOVL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x8B, r1, disp)
1.434 +#define MOVL_rspdisp_r32(disp,r1) x86_encode_r32_rspdisp32(0x8B, r1, disp)
1.435 +#define MOVL_sib_r32(ss,ii,bb,d,r1) x86_encode_r32_mem32(0x8B, r1, bb, ii, ss, d)
1.436 +#define MOVQ_imm64_r64(i64,r1) x86_encode_opcode64(0xB8, r1); OP64(i64)
1.437 +#define MOVQ_moffptr_rax(p) OP(PREF_REXW); OP(0xA1); OPPTR(p)
1.438 +#define MOVQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x89, r1, r2)
1.439 +#define MOVQ_r64_rbpdisp(r1,disp) x86_encode_r64_rbpdisp64(0x89, r1, disp)
1.440 +#define MOVQ_r64_rspdisp(r1,disp) x86_encode_r64_rspdisp64(0x89, r1, disp)
1.441 +#define MOVQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp64(0x8B, r1, disp)
1.442 +#define MOVQ_rspdisp_r64(disp,r1) x86_encode_r64_rspdisp64(0x8B, r1, disp)
1.443 +#define MOVP_immptr_rptr(p,r1) x86_encode_opcodereg( (sizeof(void*)==8 ? PREF_REXW : 0), 0xB8, r1); OPPTR(p)
1.444 +#define MOVP_moffptr_rax(p) if( sizeof(void*)==8 ) { OP(PREF_REXW); } OP(0xA1); OPPTR(p)
1.445 +#define MOVP_sib_rptr(ss,ii,bb,d,r1) x86_encode_rptr_memptr(0x8B, r1, bb, ii, ss, d)
1.446 +
1.447 +#define MOVSXL_r8_r32(r1,r2) x86_encode_r32_rm32(0x0FBE, r2, r1)
1.448 +#define MOVSXL_r16_r32(r1,r2) x86_encode_r32_rm32(0x0FBF, r2, r1)
1.449 +#define MOVSXL_rbpdisp8_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0FBE, r1, disp)
1.450 +#define MOVSXL_rbpdisp16_r32(dsp,r1) x86_encode_r32_rbpdisp32(0x0FBF, r1, dsp)
1.451 +#define MOVSXQ_imm32_r64(i32,r1) x86_encode_r64_rm64(0xC7, 0, r1); OP32(i32) /* Technically a MOV */
1.452 +#define MOVSXQ_r8_r64(r1,r2) x86_encode_r64_rm64(0x0FBE, r2, r1)
1.453 +#define MOVSXQ_r16_r64(r1,r2) x86_encode_r64_rm64(0x0FBF, r2, r1)
1.454 +#define MOVSXQ_r32_r64(r1,r2) x86_encode_r64_rm64(0x63, r2, r1)
1.455 +#define MOVSXQ_rbpdisp32_r64(dsp,r1) x86_encode_r64_rbpdisp64(0x63, r1, dsp)
1.456 +
1.457 +#define MOVZXL_r8_r32(r1,r2) x86_encode_r32_rm32(0x0FB6, r2, r1)
1.458 +#define MOVZXL_r16_r32(r1,r2) x86_encode_r32_rm32(0x0FB7, r2, r1)
1.459 +#define MOVZXL_rbpdisp8_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0FB6, r1, disp)
1.460 +#define MOVZXL_rbpdisp16_r32(dsp,r1) x86_encode_r32_rbpdisp32(0x0FB7, r1, dsp)
1.461 +
1.462 +#define MULL_r32(r1) x86_encode_r32_rm32(0xF7, 4, r1)
1.463 +#define MULL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7,4,disp)
1.464 +#define MULL_rspdisp(disp) x86_encode_r32_rspdisp32(0xF7,4,disp)
1.465 +
1.466 +#define NEGB_r8(r1) x86_encode_r32_rm32(0xF6, 3, r1)
1.467 +#define NEGL_r32(r1) x86_encode_r32_rm32(0xF7, 3, r1)
1.468 +#define NEGL_rbpdisp(r1) x86_encode_r32_rbspdisp32(0xF7, 3, disp)
1.469 +#define NEGQ_r64(r1) x86_encode_r64_rm64(0xF7, 3, r1)
1.470 +
1.471 +#define NOTB_r8(r1) x86_encode_r32_rm32(0xF6, 2, r1)
1.472 +#define NOTL_r32(r1) x86_encode_r32_rm32(0xF7, 2, r1)
1.473 +#define NOTL_rbpdisp(r1) x86_encode_r32_rbspdisp32(0xF7, 2, disp)
1.474 +#define NOTQ_r64(r1) x86_encode_r64_rm64(0xF7, 2, r1)
1.475 +
1.476 +#define ORB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 1, r1); OP(imm)
1.477 +#define ORB_r8_r8(r1,r2) x86_encode_r32_rm32(0x08, r1, r2)
1.478 +#define ORL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 1, imm, r1)
1.479 +#define ORL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,1,imm,disp)
1.480 +#define ORL_r32_r32(r1,r2) x86_encode_r32_rm32(0x09, r1, r2)
1.481 +#define ORL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x09, r1, disp)
1.482 +#define ORL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0B, r1, disp)
1.483 +#define ORQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 1, imm, r1)
1.484 +#define ORQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x09, r1, r2)
1.485 +
1.486 +#define POP_r32(r1) x86_encode_opcode32(0x58, r1)
1.487 +
1.488 +#define PUSH_imm32(imm) OP(0x68); OP32(imm)
1.489 +#define PUSH_r32(r1) x86_encode_opcode32(0x50, r1)
1.490 +
1.491 +#define RCLL_cl_r32(r1) x86_encode_r32_rm32(0xD3,2,r1)
1.492 +#define RCLL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,2,r1); } else { x86_encode_r32_rm32(0xC1,2,r1); OP(imm); }
1.493 +#define RCLQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,2,r1)
1.494 +#define RCLQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,2,r1); } else { x86_encode_r64_rm64(0xC1,2,r1); OP(imm); }
1.495 +#define RCRL_cl_r32(r1) x86_encode_r32_rm32(0xD3,3,r1)
1.496 +#define RCRL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,3,r1); } else { x86_encode_r32_rm32(0xC1,3,r1); OP(imm); }
1.497 +#define RCRQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,3,r1)
1.498 +#define RCRQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,3,r1); } else { x86_encode_r64_rm64(0xC1,3,r1); OP(imm); }
1.499 +#define ROLL_cl_r32(r1) x86_encode_r32_rm32(0xD3,0,r1)
1.500 +#define ROLL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,0,r1); } else { x86_encode_r32_rm32(0xC1,0,r1); OP(imm); }
1.501 +#define ROLQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,0,r1)
1.502 +#define ROLQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,0,r1); } else { x86_encode_r64_rm64(0xC1,0,r1); OP(imm); }
1.503 +#define RORL_cl_r32(r1) x86_encode_r32_rm32(0xD3,1,r1)
1.504 +#define RORL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,1,r1); } else { x86_encode_r32_rm32(0xC1,1,r1); OP(imm); }
1.505 +#define RORQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,1,r1)
1.506 +#define RORQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,1,r1); } else { x86_encode_r64_rm64(0xC1,1,r1); OP(imm); }
1.507 +
1.508 +#define SARL_cl_r32(r1) x86_encode_r32_rm32(0xD3,7,r1)
1.509 +#define SARL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,7,r1); } else { x86_encode_r32_rm32(0xC1,7,r1); OP(imm); }
1.510 +#define SARQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,7,r1)
1.511 +#define SARQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,7,r1); } else { x86_encode_r64_rm64(0xC1,7,r1); OP(imm); }
1.512 +#define SHLL_cl_r32(r1) x86_encode_r32_rm32(0xD3,4,r1)
1.513 +#define SHLL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,4,r1); } else { x86_encode_r32_rm32(0xC1,4,r1); OP(imm); }
1.514 +#define SHLQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,4,r1)
1.515 +#define SHLQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,4,r1); } else { x86_encode_r64_rm64(0xC1,4,r1); OP(imm); }
1.516 +#define SHRL_cl_r32(r1) x86_encode_r32_rm32(0xD3,5,r1)
1.517 +#define SHRL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,5,r1); } else { x86_encode_r32_rm32(0xC1,5,r1); OP(imm); }
1.518 +#define SHRQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,5,r1)
1.519 +#define SHRQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,5,r1); } else { x86_encode_r64_rm64(0xC1,5,r1); OP(imm); }
1.520 +
1.521 +#define SBBB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 3, r1); OP(imm)
1.522 +#define SBBB_r8_r8(r1,r2) x86_encode_r32_rm32(0x18, r1, r2)
1.523 +#define SBBL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 3, imm, r1)
1.524 +#define SBBL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,3,imm,disp)
1.525 +#define SBBL_r32_r32(r1,r2) x86_encode_r32_rm32(0x19, r1, r2)
1.526 +#define SBBL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x19, r1, disp)
1.527 +#define SBBL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x1B, r1, disp)
1.528 +#define SBBQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 3, imm, r1)
1.529 +#define SBBQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x19, r1, r2)
1.530 +
1.531 +#define SETCCB_cc_r8(cc,r1) x86_encode_r32_rm32(0x0F90+(cc), 0, r1)
1.532 +#define SETCCB_cc_rbpdisp(cc,disp) x86_encode_r32_rbpdisp32(0x0F90+(cc), 0, disp)
1.533 +
1.534 +#define STC() OP(0xF9)
1.535 +#define STD() OP(0xFD)
1.536 +
1.537 +#define SUBB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 5, r1); OP(imm)
1.538 +#define SUBB_r8_r8(r1,r2) x86_encode_r32_rm32(0x28, r1, r2)
1.539 +#define SUBL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 5, imm, r1)
1.540 +#define SUBL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,5,imm,disp)
1.541 +#define SUBL_r32_r32(r1,r2) x86_encode_r32_rm32(0x29, r1, r2)
1.542 +#define SUBL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x29, r1, disp)
1.543 +#define SUBL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x2B, r1, disp)
1.544 +#define SUBQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 5, imm, r1)
1.545 +#define SUBQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x29, r1, r2)
1.546 +
1.547 +#define TESTB_imms_r8(imm,r1) x86_encode_r32_rm32(0xF6, 0, r1); OP(imm)
1.548 +#define TESTB_r8_r8(r1,r2) x86_encode_r32_rm32(0x84, r1, r2)
1.549 +#define TESTL_imms_r32(imm,r1) x86_encode_r32_rm32(0xF7, 0, r1); OP32(imm)
1.550 +#define TESTL_imms_rbpdisp(imm,dsp) x86_encode_r32_rbpdisp32(0xF7, 0, dsp); OP32(imm)
1.551 +#define TESTL_r32_r32(r1,r2) x86_encode_r32_rm32(0x85, r1, r2)
1.552 +#define TESTL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x85, r1, disp)
1.553 +#define TESTL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x85, r1, disp) /* Same OP */
1.554 +#define TESTQ_imms_r64(imm,r1) x86_encode_r64_rm64(0xF7, 0, r1); OP32(imm)
1.555 +#define TESTQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x85, r1, r2)
1.556 +
1.557 +#define XCHGB_r8_r8(r1,r2) x86_encode_r32_rm32(0x86, r1, r2)
1.558 +#define XCHGL_r32_r32(r1,r2) x86_encode_r32_rm32(0x87, r1, r2)
1.559 +#define XCHGQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x87, r1, r2)
1.560 +
1.561 +#define XORB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 6, r1); OP(imm)
1.562 +#define XORB_r8_r8(r1,r2) x86_encode_r32_rm32(0x30, r1, r2)
1.563 +#define XORL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 6, imm, r1)
1.564 +#define XORL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,6,imm,disp)
1.565 +#define XORL_r32_r32(r1,r2) x86_encode_r32_rm32(0x31, r1, r2)
1.566 +#define XORL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x31, r1, disp)
1.567 +#define XORL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x33, r1, disp)
1.568 +#define XORQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 6, imm, r1)
1.569 +#define XORQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x31, r1, r2)
1.570 +
1.571 +/* Control flow */
1.572 +#define CALL_rel(rel) OP(0xE8); OP32(rel)
1.573 +#define CALL_imm32(ptr) x86_encode_r32_mem32disp32(0xFF, 2, -1, ptr)
1.574 +#define CALL_r32(r1) x86_encode_r32_rm32(0xFF, 2, r1)
1.575 +#define CALL_r32disp(r1,disp) x86_encode_r32_mem32disp32(0xFF, 2, r1, disp)
1.576 +
1.577 +#define JCC_cc_rel8(cc,rel) OP(0x70+(cc)); OP(rel)
1.578 +#define JCC_cc_rel32(cc,rel) OP(0x0F); OP(0x80+(cc)); OP32(rel)
1.579 +#define JCC_cc_rel(cc,rel) if( IS_INT8(rel) ) { JCC_cc_rel8(cc,(int8_t)rel); } else { JCC_cc_rel32(cc,rel); }
1.580 +
1.581 +#define JMP_rel8(rel) OP(0xEB); OP(rel)
1.582 +#define JMP_rel32(rel) OP(0xE9); OP32(rel)
1.583 +#define JMP_rel(rel) if( IS_INT8(rel) ) { JMP_rel8((int8_t)rel); } else { JMP_rel32(rel); }
1.584 +#define JMP_prerel(rel) if( IS_INT8(((int32_t)rel)-2) ) { JMP_rel8(((int8_t)rel)-2); } else { JMP_rel32(((int32_t)rel)-5); }
1.585 +#define JMP_r32(r1,disp) x86_encode_r32_rm32(0xFF, 4, r1)
1.586 +#define JMP_r32disp(r1,disp) x86_encode_r32_mem32disp32(0xFF, 4, r1, disp)
1.587 +#define RET() OP(0xC3)
1.588 +#define RET_imm(imm) OP(0xC2); OP16(imm)
1.589 +
1.590 +
1.591 +/* x87 Floating point instructions */
1.592 +#define FABS_st0() OP(0xD9); OP(0xE1)
1.593 +#define FADDP_st(st) OP(0xDE); OP(0xC0+(st))
1.594 +#define FCHS_st0() OP(0xD9); OP(0xE0)
1.595 +#define FCOMIP_st(st) OP(0xDF); OP(0xF0+(st))
1.596 +#define FDIVP_st(st) OP(0xDE); OP(0xF8+(st))
1.597 +#define FILD_r32disp(r32, disp) x86_encode_r32_mem32disp32(0xDB, 0, r32, disp)
1.598 +#define FLD0_st0() OP(0xD9); OP(0xEE);
1.599 +#define FLD1_st0() OP(0xD9); OP(0xE8);
1.600 +#define FLDCW_r32disp(r32, disp) x86_encode_r32_mem32disp32(0xD9, 5, r32, disp)
1.601 +#define FMULP_st(st) OP(0xDE); OP(0xC8+(st))
1.602 +#define FNSTCW_r32disp(r32, disp) x86_encode_r32_mem32disp32(0xD9, 7, r32, disp)
1.603 +#define FPOP_st() OP(0xDD); OP(0xC0); OP(0xD9); OP(0xF7)
1.604 +#define FSUBP_st(st) OP(0xDE); OP(0xE8+(st))
1.605 +#define FSQRT_st0() OP(0xD9); OP(0xFA)
1.606 +
1.607 +#define FILD_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xDB, 0, disp)
1.608 +#define FLDF_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD9, 0, disp)
1.609 +#define FLDD_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xDD, 0, disp)
1.610 +#define FISTP_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xDB, 3, disp)
1.611 +#define FSTPF_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD9, 3, disp)
1.612 +#define FSTPD_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xDD, 3, disp)
1.613 +
1.614 +
1.615 +/* SSE Packed floating point instructions */
1.616 +#define ADDPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F58, r1, disp)
1.617 +#define ADDPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F58, r2, r1)
1.618 +#define ANDPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F54, r1, disp)
1.619 +#define ANDPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F54, r2, r1)
1.620 +#define ANDNPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F55, r1, disp)
1.621 +#define ANDNPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F55, r2, r1)
1.622 +#define CMPPS_cc_rbpdisp_xmm(cc,d,r) x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)
1.623 +#define CMPPS_cc_xmm_xmm(cc,r1,r2) x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)
1.624 +#define DIVPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)
1.625 +#define DIVPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5E, r2, r1)
1.626 +#define MAXPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)
1.627 +#define MAXPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5F, r2, r1)
1.628 +#define MINPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)
1.629 +#define MINPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5D, r2, r1)
1.630 +#define MOV_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F28, r2, r1)
1.631 +#define MOVAPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F28, r1, disp)
1.632 +#define MOVAPS_xmm_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x0F29, r1, disp)
1.633 +#define MOVHLPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F12, r2, r1)
1.634 +#define MOVHPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F16, r1, disp)
1.635 +#define MOVHPS_xmm_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x0F17, r1, disp)
1.636 +#define MOVLHPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F16, r2, r1)
1.637 +#define MOVLPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F12, r1, disp)
1.638 +#define MOVLPS_xmm_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x0F13, r1, disp)
1.639 +#define MOVUPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F10, r1, disp)
1.640 +#define MOVUPS_xmm_rbpdisp(disp,r1) x86_encode_r32_rbpdisp32(0x0F11, r1, disp)
1.641 +#define MULPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F59, r2, r1)
1.642 +#define MULPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0xF59, r1, disp)
1.643 +#define ORPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F56, r1, disp)
1.644 +#define ORPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F56, r2, r1)
1.645 +#define RCPPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0xF53, r1, disp)
1.646 +#define RCPPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F53, r2, r1)
1.647 +#define RSQRTPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F52, r1, disp)
1.648 +#define RSQRTPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F52, r2, r1)
1.649 +#define SHUFPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0FC6, r1, disp)
1.650 +#define SHUFPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0FC6, r2, r1)
1.651 +#define SQRTPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F51, r1, disp)
1.652 +#define SQRTPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F51, r2, r1)
1.653 +#define SUBPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)
1.654 +#define SUBPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5C, r2, r1)
1.655 +#define UNPCKHPS_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F15, r1, disp)
1.656 +#define UNPCKHPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F15, r2, r1)
1.657 +#define UNPCKLPS_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F14, r1, disp)
1.658 +#define UNPCKLPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F14, r2, r1)
1.659 +#define XORPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F57, r1, disp)
1.660 +#define XORPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F57, r2, r1)
1.661 +
1.662 +/* SSE Scalar floating point instructions */
1.663 +#define ADDSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F58, r1, disp)
1.664 +#define ADDSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F58, r2, r1)
1.665 +#define CMPSS_cc_rbpdisp_xmm(cc,d,r) OP(0xF3); x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)
1.666 +#define CMPSS_cc_xmm_xmm(cc,r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)
1.667 +#define COMISS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F2F, r1, disp)
1.668 +#define COMISS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F2F, r2, r1)
1.669 +#define DIVSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)
1.670 +#define DIVSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5E, r2, r1)
1.671 +#define MAXSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)
1.672 +#define MAXSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5F, r2, r1)
1.673 +#define MINSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)
1.674 +#define MINSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5D, r2, r1)
1.675 +#define MOVSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F10, r1, disp)
1.676 +#define MOVSS_xmm_rbpdisp(r1,disp) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F11, r1, disp)
1.677 +#define MOVSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F10, r2, r1)
1.678 +#define MULSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0xF59, r1, disp)
1.679 +#define MULSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F59, r2, r1)
1.680 +#define RCPSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0xF53, r1, disp)
1.681 +#define RCPSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F53, r2, r1)
1.682 +#define RSQRTSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F52, r1, disp)
1.683 +#define RSQRTSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F52, r2, r1)
1.684 +#define SQRTSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F51, r1, disp)
1.685 +#define SQRTSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F51, r2, r1)
1.686 +#define SUBSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)
1.687 +#define SUBSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5C, r2, r1)
1.688 +#define UCOMISS_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F2E, r1, dsp)
1.689 +#define UCOMISS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F2E, r2, r1)
1.690 +
1.691 +/* SSE2 Packed floating point instructions */
1.692 +#define ADDPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F58, r1, disp)
1.693 +#define ADDPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F58, r2, r1)
1.694 +#define ANDPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F54, r1, disp)
1.695 +#define ANDPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F54, r2, r1)
1.696 +#define ANDNPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F55, r1, disp)
1.697 +#define ANDNPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F55, r2, r1)
1.698 +#define CMPPD_cc_rbpdisp_xmm(cc,d,r) OP(0x66); x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)
1.699 +#define CMPPD_cc_xmm_xmm(cc,r1,r2) OP(0x66); x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)
1.700 +#define CVTPD2PS_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5A, r1, disp)
1.701 +#define CVTPD2PS_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5A, r2, r1)
1.702 +#define CVTPS2PD_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F5A, r1, disp)
1.703 +#define CVTPS2PD_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5A, r2, r1)
1.704 +#define DIVPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)
1.705 +#define DIVPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5E, r2, r1)
1.706 +#define MAXPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)
1.707 +#define MAXPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5F, r2, r1)
1.708 +#define MINPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)
1.709 +#define MINPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5D, r2, r1)
1.710 +#define MOVHPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F16, r1, disp)
1.711 +#define MOVHPD_xmm_rbpdisp(r1,disp) OP(0x66); x86_encode_r32_rbpdisp32(0x0F17, r1, disp)
1.712 +#define MOVLPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F12, r1, disp)
1.713 +#define MOVLPD_xmm_rbpdisp(r1,disp) OP(0x66); x86_encode_r32_rbpdisp32(0x0F13, r1, disp)
1.714 +#define MULPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0xF59, r1, disp)
1.715 +#define MULPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F59, r2, r1)
1.716 +#define ORPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F56, r1, disp)
1.717 +#define ORPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F56, r2, r1)
1.718 +#define SHUFPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0FC6, r1, disp)
1.719 +#define SHUFPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0FC6, r2, r1)
1.720 +#define SUBPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)
1.721 +#define SUBPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5C, r2, r1)
1.722 +#define UNPCKHPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F15, r1, disp)
1.723 +#define UNPCKHPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F15, r2, r1)
1.724 +#define UNPCKLPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F14, r1, disp)
1.725 +#define UNPCKLPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F14, r2, r1)
1.726 +#define XORPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F57, r1, disp)
1.727 +#define XORPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F57, r2, r1)
1.728 +
1.729 +
1.730 +/* SSE2 Scalar floating point instructions */
1.731 +#define ADDSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F58, r1, disp)
1.732 +#define ADDSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F58, r2, r1)
1.733 +#define CMPSD_cc_rbpdisp_xmm(cc,d,r) OP(0xF2); x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)
1.734 +#define CMPSD_cc_xmm_xmm(cc,r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)
1.735 +#define COMISD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F2F, r1, disp)
1.736 +#define COMISD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F2F, r2, r1)
1.737 +#define DIVSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)
1.738 +#define DIVSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5E, r2, r1)
1.739 +#define MAXSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)
1.740 +#define MAXSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5F, r2, r1)
1.741 +#define MINSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)
1.742 +#define MINSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5D, r2, r1)
1.743 +#define MOVSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F10, r1, disp)
1.744 +#define MOVSD_xmm_rbpdisp(r1,disp) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F11, r1, disp)
1.745 +#define MOVSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F10, r2, r1)
1.746 +#define MULSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0xF59, r1, disp)
1.747 +#define MULSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F59, r2, r1)
1.748 +#define SQRTSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F51, r1, disp)
1.749 +#define SQRTSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F51, r2, r1)
1.750 +#define SUBSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)
1.751 +#define SUBSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5C, r2, r1)
1.752 +#define UCOMISD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F2E, r1, dsp)
1.753 +#define UCOMISD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F2E, r2, r1)
1.754 +
1.755 +/* SSE3 floating point instructions */
1.756 +#define ADDSUBPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0FD0, r1, dsp)
1.757 +#define ADDSUBPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0FD0, r2, r1)
1.758 +#define ADDSUBPS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0FD0, r1, dsp)
1.759 +#define ADDSUBPS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0FD0, r2, r1)
1.760 +#define HADDPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F7C, r1, dsp)
1.761 +#define HADDPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F7C, r2, r1)
1.762 +#define HADDPS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F7C, r1, dsp)
1.763 +#define HADDPS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F7C, r2, r1)
1.764 +#define HSUBPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F7D, r1, dsp)
1.765 +#define HSUBPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F7D, r2, r1)
1.766 +#define HSUBPS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F7D, r1, dsp)
1.767 +#define HSUBPS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F7D, r2, r1)
1.768 +#define MOVSHDUP_rbpdisp_xmm(dsp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F16, r1, dsp)
1.769 +#define MOVSHDUP_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F16, r2, r1)
1.770 +#define MOVSLDUP_rbpdisp_xmm(dsp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F12, r1, dsp)
1.771 +#define MOVSLDUP_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F12, r2, r1)
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