filename | src/asic.c |
changeset | 594:6118deafd705 |
prev | 586:2a3ba82cf243 |
next | 728:4dfc293b9d96 |
author | nkeynes |
date | Sun Jan 20 07:24:38 2008 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Fix broken asic_check_cleared_events() Handle changes to the event mask which may raise/clear an IRQ |
file | annotate | diff | log | raw |
1.1 --- a/src/asic.c Tue Jan 15 20:50:23 2008 +00001.2 +++ b/src/asic.c Sun Jan 20 07:24:38 2008 +00001.3 @@ -247,7 +247,7 @@1.4 {1.5 int i, setA = 0, setB = 0, setC = 0;1.6 uint32_t bits;1.7 - for( i=0; i<3; i++ ) {1.8 + for( i=0; i<12; i+=4 ) {1.9 bits = MMIO_READ( ASIC, PIRQ0 + i );1.10 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));1.11 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));1.12 @@ -261,6 +261,30 @@1.13 intc_clear_interrupt( INT_IRQ9 );1.14 }1.16 +void asic_event_mask_changed( )1.17 +{1.18 + int i, setA = 0, setB = 0, setC = 0;1.19 + uint32_t bits;1.20 + for( i=0; i<12; i+=4 ) {1.21 + bits = MMIO_READ( ASIC, PIRQ0 + i );1.22 + setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));1.23 + setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));1.24 + setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));1.25 + }1.26 + if( setA == 0 )1.27 + intc_clear_interrupt( INT_IRQ13 );1.28 + else1.29 + intc_raise_interrupt( INT_IRQ13 );1.30 + if( setB == 0 )1.31 + intc_clear_interrupt( INT_IRQ11 );1.32 + else1.33 + intc_raise_interrupt( INT_IRQ11 );1.34 + if( setC == 0 )1.35 + intc_clear_interrupt( INT_IRQ9 );1.36 + else1.37 + intc_raise_interrupt( INT_IRQ9 );1.38 +}1.39 +1.40 void g2_dma_transfer( int channel )1.41 {1.42 uint32_t offset = channel << 5;1.43 @@ -345,6 +369,18 @@1.44 }1.45 asic_check_cleared_events();1.46 break;1.47 + case IRQA0:1.48 + case IRQA1:1.49 + case IRQA2:1.50 + case IRQB0:1.51 + case IRQB1:1.52 + case IRQB2:1.53 + case IRQC0:1.54 + case IRQC1:1.55 + case IRQC2:1.56 + MMIO_WRITE( ASIC, reg, val );1.57 + asic_event_mask_changed();1.58 + break;1.59 case SYSRESET:1.60 if( val == 0x7611 ) {1.61 dreamcast_reset();
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