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lxdream.org :: lxdream/src/pvr2/pvr2.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 189:615b70cfd729
prev161:408b9210395f
next191:df4441cf3128
author nkeynes
date Wed Aug 02 04:06:45 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Issue 0003: TA Vertex compiler
Initial implementation of the TA.
Renderer hooked up to the TA "properly" now as well
file annotate diff log raw
1.1 --- a/src/pvr2/pvr2.c Sun Jun 18 11:57:05 2006 +0000
1.2 +++ b/src/pvr2/pvr2.c Wed Aug 02 04:06:45 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: pvr2.c,v 1.27 2006-06-18 11:57:05 nkeynes Exp $
1.6 + * $Id: pvr2.c,v 1.28 2006-08-02 04:06:45 nkeynes Exp $
1.7 *
1.8 * PVR2 (Video) Core module implementation and MMIO registers.
1.9 *
1.10 @@ -214,32 +214,63 @@
1.11 return;
1.12 }
1.13
1.14 - if( reg == PVRID ) {
1.15 - ERROR( "Write attempted to readonly register PVRID: ", val );
1.16 - return;
1.17 - }
1.18 -
1.19 - MMIO_WRITE( PVR2, reg, val );
1.20 -
1.21 switch(reg) {
1.22 + case PVRID:
1.23 + case PVRVER:
1.24 + case GUNPOS:
1.25 + case TA_POLYPOS:
1.26 + case TA_LISTPOS:
1.27 + /* Readonly registers */
1.28 + break;
1.29 + case RENDSTART:
1.30 + if( val == 0xFFFFFFFF )
1.31 + pvr2_render_scene();
1.32 + break;
1.33 case DISPADDR1:
1.34 + val &= 0x00FFFFFC;
1.35 + MMIO_WRITE( PVR2, reg, val );
1.36 if( pvr2_state.retrace ) {
1.37 pvr2_display_frame();
1.38 pvr2_state.retrace = FALSE;
1.39 }
1.40 break;
1.41 + case HCLIP:
1.42 + MMIO_WRITE( PVR2, reg, val & 0x07FF07FF );
1.43 + break;
1.44 + case VCLIP:
1.45 + MMIO_WRITE( PVR2, reg, val & 0x03FF03FF );
1.46 + break;
1.47 + case HPOS_IRQ:
1.48 + MMIO_WRITE( PVR2, reg, val & 0x03FF33FF );
1.49 + break;
1.50 case VPOS_IRQ:
1.51 - pvr2_state.irq_vpos1 = (val >> 16) & 0x03FF;
1.52 + val = val & 0x03FF03FF;
1.53 + pvr2_state.irq_vpos1 = (val >> 16);
1.54 pvr2_state.irq_vpos2 = val & 0x03FF;
1.55 + MMIO_WRITE( PVR2, reg, val );
1.56 break;
1.57 - case TAINIT:
1.58 + case TA_TILEBASE:
1.59 + case TA_TILEEND:
1.60 + case TA_LISTBASE:
1.61 + MMIO_WRITE( PVR2, reg, val & 0x00FFFFE0 );
1.62 + break;
1.63 + case TA_POLYBASE:
1.64 + case TA_POLYEND:
1.65 + MMIO_WRITE( PVR2, reg, val & 0x00FFFFFC );
1.66 + break;
1.67 + case TA_TILESIZE:
1.68 + MMIO_WRITE( PVR2, reg, val & 0x000F003F );
1.69 + break;
1.70 + case TA_TILECFG:
1.71 + MMIO_WRITE( PVR2, reg, val & 0x00133333 );
1.72 + break;
1.73 + case TA_INIT:
1.74 if( val & 0x80000000 )
1.75 pvr2_ta_init();
1.76 break;
1.77 - case RENDSTART:
1.78 - if( val == 0xFFFFFFFF )
1.79 - pvr2_render_scene();
1.80 - break;
1.81 +
1.82 + default:
1.83 + MMIO_WRITE( PVR2, reg, val );
1.84 }
1.85 }
1.86
1.87 @@ -270,7 +301,7 @@
1.88
1.89 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
1.90 {
1.91 - pvr2_ta_write( &val, sizeof(uint32_t) );
1.92 + pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
1.93 }
1.94
1.95
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