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lxdream 0.9.1
released Jun 29
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filename src/aica/armcore.c
changeset 49:6290c467cfbd
prev46:30d123047e16
next51:ed6c27067502
author nkeynes
date Tue Dec 27 12:42:29 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Implement missing DP instructions
Add UNIMP() on all non-DP instructions in the DP block
file annotate diff log raw
1.1 --- a/src/aica/armcore.c Tue Dec 27 08:42:57 2005 +0000
1.2 +++ b/src/aica/armcore.c Tue Dec 27 12:42:29 2005 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: armcore.c,v 1.10 2005-12-27 08:42:57 nkeynes Exp $
1.6 + * $Id: armcore.c,v 1.11 2005-12-27 12:42:29 nkeynes Exp $
1.7 *
1.8 * ARM7TDMI CPU emulation core.
1.9 *
1.10 @@ -658,7 +658,7 @@
1.11 {
1.12 uint32_t pc = PC;
1.13 uint32_t ir = MEM_READ_LONG(pc);
1.14 - uint32_t operand, operand2, tmp, cond;
1.15 + uint32_t operand, operand2, tmp, tmp2, cond;
1.16
1.17 pc += 4;
1.18 PC = pc;
1.19 @@ -757,6 +757,7 @@
1.20 }
1.21 } else if( (ir & 0x0E000090) == 0x00000090 ) {
1.22 /* Neither are these */
1.23 + UNIMP(ir);
1.24 switch( (ir>>5)&0x03 ) {
1.25 case 0:
1.26 /* Arithmetic extension area */
1.27 @@ -799,20 +800,21 @@
1.28 } else {
1.29 /* STRH */
1.30 }
1.31 + UNIMP(ir);
1.32 break;
1.33 case 2:
1.34 if( LFLAG(ir) ) {
1.35 /* LDRSB */
1.36 } else {
1.37 - UNIMP(ir);
1.38 }
1.39 + UNIMP(ir);
1.40 break;
1.41 case 3:
1.42 if( LFLAG(ir) ) {
1.43 /* LDRSH */
1.44 } else {
1.45 - UNIMP(ir);
1.46 }
1.47 + UNIMP(ir);
1.48 break;
1.49 }
1.50 } else {
1.51 @@ -899,11 +901,65 @@
1.52 }
1.53 break;
1.54 case 10: /* ADC */
1.55 + LRD(ir) = RN(ir) + arm_get_shift_operand(ir) +
1.56 + (armr.c ? 1 : 0);
1.57 + break;
1.58 case 11: /* ADCS */
1.59 + operand = arm_get_shift_operand(ir);
1.60 + operand2 = RN(ir);
1.61 + tmp = operand + operand2;
1.62 + tmp2 = tmp + armr.c ? 1 : 0;
1.63 + LRD(ir) = tmp2;
1.64 + if( RDn(ir) == 15 ) {
1.65 + arm_restore_cpsr();
1.66 + } else {
1.67 + armr.n = tmp >> 31;
1.68 + armr.z = (tmp == 0 );
1.69 + armr.c = IS_CARRY(tmp,operand,operand2) ||
1.70 + (tmp2 < tmp);
1.71 + armr.v = IS_ADDOVERFLOW(tmp,operand, operand2) ||
1.72 + ((tmp&0x80000000) != (tmp2&0x80000000));
1.73 + }
1.74 + break;
1.75 case 12: /* SBC */
1.76 + LRD(ir) = RN(ir) - arm_get_shift_operand(ir) -
1.77 + (armr.c ? 0 : 1);
1.78 + break;
1.79 case 13: /* SBCS */
1.80 + operand = RN(ir);
1.81 + operand2 = arm_get_shift_operand(ir);
1.82 + tmp = operand - operand2;
1.83 + tmp2 = tmp - (armr.c ? 0 : 1);
1.84 + if( RDn(ir) == 15 ) {
1.85 + arm_restore_cpsr();
1.86 + } else {
1.87 + armr.n = tmp >> 31;
1.88 + armr.z = (tmp == 0 );
1.89 + armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
1.90 + (tmp2<tmp);
1.91 + armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||
1.92 + ((tmp&0x80000000) != (tmp2&0x80000000));
1.93 + }
1.94 + break;
1.95 case 14: /* RSC */
1.96 + LRD(ir) = arm_get_shift_operand(ir) - RN(ir) -
1.97 + (armr.c ? 0 : 1);
1.98 + break;
1.99 case 15: /* RSCS */
1.100 + operand = arm_get_shift_operand(ir);
1.101 + operand2 = RN(ir);
1.102 + tmp = operand - operand2;
1.103 + tmp2 = tmp - (armr.c ? 0 : 1);
1.104 + if( RDn(ir) == 15 ) {
1.105 + arm_restore_cpsr();
1.106 + } else {
1.107 + armr.n = tmp >> 31;
1.108 + armr.z = (tmp == 0 );
1.109 + armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
1.110 + (tmp2<tmp);
1.111 + armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||
1.112 + ((tmp&0x80000000) != (tmp2&0x80000000));
1.113 + }
1.114 break;
1.115 case 17: /* TST Rn, operand */
1.116 operand = arm_get_shift_operand_s(ir) & RN(ir);
.