1.1 --- a/src/sh4/sh4.c Wed Oct 29 23:32:28 2008 +0000
1.2 +++ b/src/sh4/sh4.c Fri Oct 31 01:07:44 2008 +0000
1.4 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
1.7 -void sh4_switch_fr_banks()
1.8 +void FASTCALL sh4_switch_fr_banks()
1.11 for( i=0; i<16; i++ ) {
1.16 -void sh4_write_sr( uint32_t newval )
1.17 +void FASTCALL sh4_write_sr( uint32_t newval )
1.19 int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
1.20 int newbank = (newval&SR_MDRB) == SR_MDRB;
1.22 intc_mask_changed();
1.25 -void sh4_write_fpscr( uint32_t newval )
1.26 +void FASTCALL sh4_write_fpscr( uint32_t newval )
1.28 if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
1.29 sh4_switch_fr_banks();
1.31 sh4r.fpscr = newval & FPSCR_MASK;
1.34 -uint32_t sh4_read_sr( void )
1.35 +uint32_t FASTCALL sh4_read_sr( void )
1.37 /* synchronize sh4r.sr with the various bitflags */
1.38 sh4r.sr &= SR_MQSTMASK;
1.40 * Raise a general CPU exception for the specified exception code.
1.41 * (NOT for TRAPA or TLB exceptions)
1.43 -gboolean sh4_raise_exception( int code )
1.44 +gboolean FASTCALL sh4_raise_exception( int code )
1.46 RAISE( code, EXV_EXCEPTION );
1.50 * Raise a CPU reset exception with the specified exception code.
1.52 -gboolean sh4_raise_reset( int code )
1.53 +gboolean FASTCALL sh4_raise_reset( int code )
1.55 // FIXME: reset modules as per "manual reset"
1.57 @@ -404,13 +404,13 @@
1.61 -gboolean sh4_raise_trap( int trap )
1.62 +gboolean FASTCALL sh4_raise_trap( int trap )
1.64 MMIO_WRITE( MMU, TRA, trap<<2 );
1.65 RAISE( EXC_TRAP, EXV_EXCEPTION );
1.68 -gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
1.69 +gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
1.70 if( sh4r.in_delay_slot ) {
1.71 return sh4_raise_exception(slot_code);
1.73 @@ -418,12 +418,12 @@
1.77 -gboolean sh4_raise_tlb_exception( int code )
1.78 +gboolean FASTCALL sh4_raise_tlb_exception( int code )
1.80 RAISE( code, EXV_TLBMISS );
1.83 -void sh4_accept_interrupt( void )
1.84 +void FASTCALL sh4_accept_interrupt( void )
1.86 uint32_t code = intc_accept_interrupt();
1.87 sh4r.ssr = sh4_read_sr();
1.89 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
1.92 -void signsat48( void )
1.93 +void FASTCALL signsat48( void )
1.95 if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
1.96 sh4r.mac = 0xFFFF800000000000LL;
1.98 sh4r.mac = 0x00007FFFFFFFFFFFLL;
1.101 -void sh4_fsca( uint32_t anglei, float *fr )
1.102 +void FASTCALL sh4_fsca( uint32_t anglei, float *fr )
1.104 float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
1.105 *fr++ = cosf(angle);
1.106 @@ -456,7 +456,7 @@
1.107 * Sets sh4_state appropriately and ensures any stopping peripheral modules
1.110 -void sh4_sleep(void)
1.111 +void FASTCALL sh4_sleep(void)
1.113 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
1.114 sh4r.sh4_state = SH4_STATE_STANDBY;
1.115 @@ -523,7 +523,7 @@
1.116 * Compute the matrix tranform of fv given the matrix xf.
1.117 * Both fv and xf are word-swapped as per the sh4r.fr banks
1.119 -void sh4_ftrv( float *target )
1.120 +void FASTCALL sh4_ftrv( float *target )
1.122 float fv[4] = { target[1], target[0], target[3], target[2] };
1.123 target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +