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tree revision 926:68f3e0fe02f1
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filename src/sh4/sh4x86.in
changeset 926:68f3e0fe02f1
prev911:2f6ba75b84d1
next927:17b6b9e245d8
author nkeynes
date Sun Dec 14 07:50:48 2008 +0000 (13 years ago)
permissions -rw-r--r--
last change Setup a 'proper' stackframe in translated blocks. This doesn't affect performance noticeably,
but does ensure that
a) The stack is aligned correctly on OS X with no extra effort, and
b) We can't mess up the stack and crash that way anymore.
Replace all PUSH/POP instructions (outside of prologue/epilogue) with ESP-rel moves to stack
local variables.
Finally merge ia32mac and ia32abi together, since they're pretty much the same now anyway (and
thereby simplifying maintenance a good deal)
file annotate diff log raw 
     1.1 --- a/src/sh4/sh4x86.in	Fri Oct 31 02:57:59 2008 +0000

     1.2 +++ b/src/sh4/sh4x86.in	Sun Dec 14 07:50:48 2008 +0000

     1.3 @@ -315,12 +315,8 @@

     1.4  #if SIZEOF_VOID_P == 8

     1.5  #include "sh4/ia64abi.h"

     1.6  #else /* 32-bit system */

     1.7 -#ifdef APPLE_BUILD

     1.8 -#include "sh4/ia32mac.h"

     1.9 -#else

    1.10  #include "sh4/ia32abi.h"

    1.11  #endif

    1.12 -#endif

    1.13  

    1.14  void sh4_translate_begin_block( sh4addr_t pc ) 

    1.15  {

    1.16 @@ -390,9 +386,7 @@

    1.17      } else {

    1.18  	call_func1(xlat_get_code,R_EAX);

    1.19      }

    1.20 -    AND_imm8s_rptr( 0xFC, R_EAX );

    1.21 -    POP_r32(R_EBP);

    1.22 -    RET();

    1.23 +    exit_block();

    1.24  } 

    1.25  

    1.26  /**

    1.27 @@ -473,9 +467,9 @@

    1.28      load_spreg( R_ECX, R_GBR );

    1.29      ADD_r32_r32( R_ECX, R_EAX );

    1.30      MMU_TRANSLATE_WRITE( R_EAX );

    1.31 -    PUSH_realigned_r32(R_EAX);

    1.32 +    MOV_r32_esp8(R_EAX, 0);

    1.33      MEM_READ_BYTE( R_EAX, R_EDX );

    1.34 -    POP_realigned_r32(R_EAX);

    1.35 +    MOV_esp8_r32(0, R_EAX);

    1.36      AND_imm32_r32(imm, R_EDX );

    1.37      MEM_WRITE_BYTE( R_EAX, R_EDX );

    1.38      sh4_x86.tstate = TSTATE_NONE;

    1.39 @@ -662,10 +656,10 @@

    1.40  	load_reg( R_EAX, Rm );

    1.41  	check_ralign32( R_EAX );

    1.42  	MMU_TRANSLATE_READ( R_EAX );

    1.43 -	PUSH_realigned_r32( R_EAX );

    1.44 +	MOV_r32_esp8(R_EAX, 0);

    1.45  	load_reg( R_EAX, Rn );

    1.46  	ADD_imm8s_r32( 4, R_EAX );

    1.47 -	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );

    1.48 +	MMU_TRANSLATE_READ( R_EAX );

    1.49  	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );

    1.50  	// Note translate twice in case of page boundaries. Maybe worth

    1.51  	// adding a page-boundary check to skip the second translation

    1.52 @@ -673,19 +667,18 @@

    1.53  	load_reg( R_EAX, Rm );

    1.54  	check_ralign32( R_EAX );

    1.55  	MMU_TRANSLATE_READ( R_EAX );

    1.56 -	load_reg( R_ECX, Rn );

    1.57 -	check_ralign32( R_ECX );

    1.58 -	PUSH_realigned_r32( R_EAX );

    1.59 -	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );

    1.60 -	MOV_r32_r32( R_ECX, R_EAX );

    1.61 +	MOV_r32_esp8( R_EAX, 0 );

    1.62 +	load_reg( R_EAX, Rn );

    1.63 +	check_ralign32( R_EAX );

    1.64 +	MMU_TRANSLATE_READ( R_EAX );

    1.65  	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );

    1.66  	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );

    1.67      }

    1.68      MEM_READ_LONG( R_EAX, R_EAX );

    1.69 -    POP_r32( R_ECX );

    1.70 -    PUSH_r32( R_EAX );

    1.71 -    MEM_READ_LONG( R_ECX, R_EAX );

    1.72 -    POP_realigned_r32( R_ECX );

    1.73 +    MOV_r32_esp8( R_EAX, 4 );

    1.74 +    MOV_esp8_r32( 0, R_EAX );

    1.75 +    MEM_READ_LONG( R_EAX, R_EAX );

    1.76 +    MOV_esp8_r32( 4, R_ECX );

    1.77  

    1.78      IMUL_r32( R_ECX );

    1.79      ADD_r32_sh4r( R_EAX, R_MACL );

    1.80 @@ -704,10 +697,10 @@

    1.81  	load_reg( R_EAX, Rm );

    1.82  	check_ralign16( R_EAX );

    1.83  	MMU_TRANSLATE_READ( R_EAX );

    1.84 -	PUSH_realigned_r32( R_EAX );

    1.85 +        MOV_r32_esp8( R_EAX, 0 );

    1.86  	load_reg( R_EAX, Rn );

    1.87  	ADD_imm8s_r32( 2, R_EAX );

    1.88 -	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );

    1.89 +	MMU_TRANSLATE_READ( R_EAX );

    1.90  	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );

    1.91  	// Note translate twice in case of page boundaries. Maybe worth

    1.92  	// adding a page-boundary check to skip the second translation

    1.93 @@ -715,21 +708,20 @@

    1.94  	load_reg( R_EAX, Rm );

    1.95  	check_ralign16( R_EAX );

    1.96  	MMU_TRANSLATE_READ( R_EAX );

    1.97 -	load_reg( R_ECX, Rn );

    1.98 -	check_ralign16( R_ECX );

    1.99 -	PUSH_realigned_r32( R_EAX );

   1.100 -	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );

   1.101 -	MOV_r32_r32( R_ECX, R_EAX );

   1.102 +        MOV_r32_esp8( R_EAX, 0 );

   1.103 +	load_reg( R_EAX, Rn );

   1.104 +	check_ralign16( R_EAX );

   1.105 +	MMU_TRANSLATE_READ( R_EAX );

   1.106  	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );

   1.107  	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );

   1.108      }

   1.109      MEM_READ_WORD( R_EAX, R_EAX );

   1.110 -    POP_r32( R_ECX );

   1.111 -    PUSH_r32( R_EAX );

   1.112 -    MEM_READ_WORD( R_ECX, R_EAX );

   1.113 -    POP_realigned_r32( R_ECX );

   1.114 +    MOV_r32_esp8( R_EAX, 4 );

   1.115 +    MOV_esp8_r32( 0, R_EAX );

   1.116 +    MEM_READ_WORD( R_EAX, R_EAX );

   1.117 +    MOV_esp8_r32( 4, R_ECX );

   1.118 +

   1.119      IMUL_r32( R_ECX );

   1.120 -

   1.121      load_spreg( R_ECX, R_S );

   1.122      TEST_r32_r32( R_ECX, R_ECX );

   1.123      JE_rel8( nosat );

   1.124 @@ -830,9 +822,9 @@

   1.125      load_spreg( R_ECX, R_GBR );

   1.126      ADD_r32_r32( R_ECX, R_EAX );

   1.127      MMU_TRANSLATE_WRITE( R_EAX );

   1.128 -    PUSH_realigned_r32(R_EAX);

   1.129 +    MOV_r32_esp8( R_EAX, 0 );

   1.130      MEM_READ_BYTE( R_EAX, R_EDX );

   1.131 -    POP_realigned_r32(R_EAX);

   1.132 +    MOV_esp8_r32( 0, R_EAX );

   1.133      OR_imm32_r32(imm, R_EDX );

   1.134      MEM_WRITE_BYTE( R_EAX, R_EDX );

   1.135      sh4_x86.tstate = TSTATE_NONE;

   1.136 @@ -1049,12 +1041,12 @@

   1.137      COUNT_INST(I_TASB);

   1.138      load_reg( R_EAX, Rn );

   1.139      MMU_TRANSLATE_WRITE( R_EAX );

   1.140 -    PUSH_realigned_r32( R_EAX );

   1.141 +    MOV_r32_esp8( R_EAX, 0 );

   1.142      MEM_READ_BYTE( R_EAX, R_EDX );

   1.143      TEST_r8_r8( R_DL, R_DL );

   1.144      SETE_t();

   1.145      OR_imm8_r8( 0x80, R_DL );

   1.146 -    POP_realigned_r32( R_EAX );

   1.147 +    MOV_esp8_r32( 0, R_EAX );

   1.148      MEM_WRITE_BYTE( R_EAX, R_EDX );

   1.149      sh4_x86.tstate = TSTATE_NONE;

   1.150  :}

   1.151 @@ -1105,9 +1097,9 @@

   1.152      load_spreg( R_ECX, R_GBR );

   1.153      ADD_r32_r32( R_ECX, R_EAX );

   1.154      MMU_TRANSLATE_WRITE( R_EAX );

   1.155 -    PUSH_realigned_r32(R_EAX);

   1.156 +    MOV_r32_esp8( R_EAX, 0 );

   1.157      MEM_READ_BYTE(R_EAX, R_EDX);

   1.158 -    POP_realigned_r32(R_EAX);

   1.159 +    MOV_esp8_r32( 0, R_EAX );

   1.160      XOR_imm32_r32( imm, R_EDX );

   1.161      MEM_WRITE_BYTE( R_EAX, R_EDX );

   1.162      sh4_x86.tstate = TSTATE_NONE;

   1.163 @@ -2636,11 +2628,12 @@

   1.164      check_walign32( R_EAX );

   1.165      ADD_imm8s_r32( -4, R_EAX );

   1.166      MMU_TRANSLATE_WRITE( R_EAX );

   1.167 -    PUSH_realigned_r32( R_EAX );

   1.168 +    MOV_r32_esp8( R_EAX, 0 );

   1.169      call_func0( sh4_read_sr );

   1.170 -    POP_realigned_r32( R_ECX );

   1.171 +    MOV_r32_r32( R_EAX, R_EDX );

   1.172 +    MOV_esp8_r32( 0, R_EAX );

   1.173      ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );

   1.174 -    MEM_WRITE_LONG( R_ECX, R_EAX );

   1.175 +    MEM_WRITE_LONG( R_EAX, R_EDX );

   1.176      sh4_x86.tstate = TSTATE_NONE;

   1.177  :}

   1.178  STC.L VBR, @-Rn {:
.