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lxdream.org :: lxdream/src/sh4/sh4mmio.h :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.h
changeset 826:69f2c9f1e608
prev819:ef4fec10a63a
next841:808d64b05073
author nkeynes
date Sun Aug 24 02:43:28 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix mask correctness of MMU/general IO registers, add unknown/undoced
register at FF00002C
file annotate diff log raw
1.1 --- a/src/sh4/sh4mmio.h Tue Aug 19 22:58:05 2008 +0000
1.2 +++ b/src/sh4/sh4mmio.h Sun Aug 24 02:43:28 2008 +0000
1.3 @@ -1,6 +1,6 @@
1.4 /**
1.5 * $Id$
1.6 - *
1.7 + *
1.8 * MMIO region and supporting function declarations. Private to the sh4
1.9 * module.
1.10 *
1.11 @@ -46,6 +46,7 @@
1.12 LONG_PORT( 0x020, TRA, PORT_MRW, UNDEFINED, "TRAPA exception register" )
1.13 LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" )
1.14 LONG_PORT( 0x028, INTEVT,PORT_MRW, UNDEFINED, "Interrupt event register" )
1.15 + LONG_PORT( 0x02C, MMUUNK1, PORT_MRW, 0, "Unknown MMU/general register" )
1.16 LONG_PORT( 0x030, SH4VER, PORT_MRW, 0x040205C1, "SH4 version register (PVR)" ) /* Renamed to avoid naming conflict */
1.17 LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" )
1.18 LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" )
1.19 @@ -56,10 +57,10 @@
1.20
1.21 /* Performance counter values (undocumented) */
1.22 MMIO_REGION_BEGIN( 0xFF100000, PMM, "Performance monitoring" )
1.23 - LONG_PORT (0x004, PMCTR1H, PORT_MR, 0, "Performance counter 1 High" )
1.24 - LONG_PORT (0x008, PMCTR1L, PORT_MR, 0, "Performance counter 1 Low" )
1.25 - LONG_PORT (0x00C, PMCTR2H, PORT_MR, 0, "Performance counter 2 High" )
1.26 - LONG_PORT (0x010, PMCTR2L, PORT_MR, 0, "Performance counter 2 Low" )
1.27 + LONG_PORT( 0x004, PMCTR1H, PORT_MR, 0, "Performance counter 1 High" )
1.28 + LONG_PORT( 0x008, PMCTR1L, PORT_MR, 0, "Performance counter 1 Low" )
1.29 + LONG_PORT( 0x00C, PMCTR2H, PORT_MR, 0, "Performance counter 2 High" )
1.30 + LONG_PORT( 0x010, PMCTR2L, PORT_MR, 0, "Performance counter 2 Low" )
1.31 MMIO_REGION_END
1.32
1.33 /* User Break Controller (Page 717 [757] of sh7750h manual) */
1.34 @@ -173,7 +174,7 @@
1.35 BYTE_PORT( 0x004, SCBRR2, PORT_MRW, 0xFF, "Bit rate register (FIFO)" )
1.36 WORD_PORT( 0x008, SCSCR2, PORT_MRW, 0x0000, "Serial control register" )
1.37 BYTE_PORT( 0x00C, SCFTDR2, PORT_W, UNDEFINED, "Transmit FIFO data register" )
1.38 - WORD_PORT( 0x010, SCFSR2, PORT_MRW, 0x0060, "Serial status register (FIFO)")
1.39 + WORD_PORT( 0x010, SCFSR2, PORT_MRW, 0x0060, "Serial status register (FIFO)" )
1.40 BYTE_PORT( 0x014, SCFRDR2, PORT_R, UNDEFINED, "Receive FIFO data register" )
1.41 WORD_PORT( 0x018, SCFCR2, PORT_MRW, 0x0000, "FIFO control register" )
1.42 WORD_PORT( 0x01C, SCFDR2, PORT_MR, 0x0000, "FIFO data count register" )
.