lxdream 0.9.1| filename | src/sh4/sh4core.in |
| changeset | 939:6f2302afeb89 |
| prev | 927:17b6b9e245d8 |
| next | 945:787729653236 |
| author | nkeynes |
| date | Sat Jan 03 03:30:26 2009 +0000 (15 years ago) |
| branch | lxdream-mem |
| permissions | -rw-r--r-- |
| last change | MMU work-in-progress * Move SDRAM out into separate sdram.c * Move all page-table management into mmu.c * Convert UTLB management to use the new page-tables * Rip out all calls to mmu_vma_to_phys_* and replace with direct access |
| file | annotate | diff | log | raw |
1.1 --- a/src/sh4/sh4core.in Mon Dec 15 10:44:56 2008 +00001.2 +++ b/src/sh4/sh4core.in Sat Jan 03 03:30:26 2009 +00001.3 @@ -164,23 +164,30 @@1.4 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }1.5 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)1.7 +#define ADDRSPACE (IS_SH4_PRIVMODE() ? sh4_address_space : sh4_user_address_space)1.8 +#define SQADDRSPACE (IS_SH4_PRIVMODE() ? storequeue_address_space : storequeue_user_address_space)1.9 +1.10 #ifdef HAVE_FRAME_ADDRESS1.11 static FASTCALL __attribute__((noinline)) void *__first_arg(void *a, void *b) { return a; }1.12 #define INIT_EXCEPTIONS(label) goto *__first_arg(&&fnstart,&&label); fnstart:1.13 -#define MMU_TRANSLATE_READ( addr ) memtmp = mmu_vma_to_phys_read(addr, &&except )1.14 -#define MMU_TRANSLATE_WRITE( addr ) memtmp = mmu_vma_to_phys_write(addr, &&except )1.15 +#define MEM_READ_BYTE( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_byte)((addr), &&except)1.16 +#define MEM_READ_WORD( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_word)((addr), &&except)1.17 +#define MEM_READ_LONG( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_long)((addr), &&except)1.18 +#define MEM_WRITE_BYTE( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_byte)((addr), (val), &&except)1.19 +#define MEM_WRITE_WORD( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_word)((addr), (val), &&except)1.20 +#define MEM_WRITE_LONG( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_long)((addr), (val), &&except)1.21 #else1.22 #define INIT_EXCEPTIONS(label)1.23 -#define MMU_TRANSLATE_READ( addr ) if( (memtmp = mmu_vma_to_phys_read(addr)) == MMU_VMA_ERROR ) { return TRUE; }1.24 -#define MMU_TRANSLATE_WRITE( addr ) if( (memtmp = mmu_vma_to_phys_write(addr)) == MMU_VMA_ERROR ) { return TRUE; }1.25 +#define MEM_READ_BYTE( addr, val ) val = ADDRSPACE[(addr)>>12]->read_byte(addr)1.26 +#define MEM_READ_WORD( addr, val ) val = ADDRSPACE[(addr)>>12]->read_word(addr)1.27 +#define MEM_READ_LONG( addr, val ) val = ADDRSPACE[(addr)>>12]->read_long(addr)1.28 +#define MEM_WRITE_BYTE( addr, val ) ADDRSPACE[(addr)>>12]->write_byte(addr, val)1.29 +#define MEM_WRITE_WORD( addr, val ) ADDRSPACE[(addr)>>12]->write_word(addr, val)1.30 +#define MEM_WRITE_LONG( addr, val ) ADDRSPACE[(addr)>>12]->write_long(addr, val)1.31 #endif1.33 -#define MEM_READ_BYTE( addr, val ) MMU_TRANSLATE_READ(addr); val = sh4_read_byte(memtmp)1.34 -#define MEM_READ_WORD( addr, val ) MMU_TRANSLATE_READ(addr); val = sh4_read_word(memtmp)1.35 -#define MEM_READ_LONG( addr, val ) MMU_TRANSLATE_READ(addr); val = sh4_read_long(memtmp)1.36 -#define MEM_WRITE_BYTE( addr, val ) MMU_TRANSLATE_WRITE(addr); sh4_write_byte(memtmp, val)1.37 -#define MEM_WRITE_WORD( addr, val ) MMU_TRANSLATE_WRITE(addr); sh4_write_word(memtmp, val)1.38 -#define MEM_WRITE_LONG( addr, val ) MMU_TRANSLATE_WRITE(addr); sh4_write_long(memtmp, val)1.39 +1.40 +1.43 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)1.44 @@ -188,34 +195,30 @@1.45 #define MEM_FP_READ( addr, reg ) \1.46 if( IS_FPU_DOUBLESIZE() ) { \1.47 CHECKRALIGN64(addr); \1.48 - MMU_TRANSLATE_READ(addr); \1.49 if( reg & 1 ) { \1.50 - *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(memtmp); \1.51 - *((uint32_t *)&XF(reg)) = sh4_read_long(memtmp+4); \1.52 + MEM_READ_LONG( addr, *((uint32_t *)&XF((reg) & 0x0E)) ); \1.53 + MEM_READ_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \1.54 } else { \1.55 - *((uint32_t *)&FR(reg)) = sh4_read_long(memtmp); \1.56 - *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(memtmp+4); \1.57 + MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \1.58 + MEM_READ_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \1.59 } \1.60 } else { \1.61 CHECKRALIGN32(addr); \1.62 - MMU_TRANSLATE_READ(addr); \1.63 - *((uint32_t *)&FR(reg)) = sh4_read_long(memtmp); \1.64 + MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \1.65 }1.66 #define MEM_FP_WRITE( addr, reg ) \1.67 if( IS_FPU_DOUBLESIZE() ) { \1.68 CHECKWALIGN64(addr); \1.69 - MMU_TRANSLATE_WRITE(addr); \1.70 if( reg & 1 ) { \1.71 - sh4_write_long( memtmp, *((uint32_t *)&XF((reg)&0x0E)) ); \1.72 - sh4_write_long( memtmp+4, *((uint32_t *)&XF(reg)) ); \1.73 + MEM_WRITE_LONG( addr, *((uint32_t *)&XF((reg)&0x0E)) ); \1.74 + MEM_WRITE_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \1.75 } else { \1.76 - sh4_write_long( memtmp, *((uint32_t *)&FR(reg)) ); \1.77 - sh4_write_long( memtmp+4, *((uint32_t *)&FR((reg)|0x01)) ); \1.78 + MEM_WRITE_LONG( addr, *((uint32_t *)&FR(reg)) ); \1.79 + MEM_WRITE_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \1.80 } \1.81 } else { \1.82 CHECKWALIGN32(addr); \1.83 - MMU_TRANSLATE_WRITE(addr); \1.84 - sh4_write_long( memtmp, *((uint32_t *)&FR((reg))) ); \1.85 + MEM_WRITE_LONG(addr, *((uint32_t *)&FR((reg))) ); \1.86 }1.88 gboolean sh4_execute_instruction( void )
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