filename | src/sh4/sh4x86.in |
changeset | 939:6f2302afeb89 |
prev | 937:81b0c79d9788 |
next | 941:c67574ed4355 |
author | nkeynes |
date | Sat Jan 03 03:30:26 2009 +0000 (15 years ago) |
branch | lxdream-mem |
permissions | -rw-r--r-- |
last change | MMU work-in-progress * Move SDRAM out into separate sdram.c * Move all page-table management into mmu.c * Convert UTLB management to use the new page-tables * Rip out all calls to mmu_vma_to_phys_* and replace with direct access |
file | annotate | diff | log | raw |
1.1 --- a/src/sh4/sh4x86.in Sat Dec 27 03:14:59 2008 +00001.2 +++ b/src/sh4/sh4x86.in Sat Jan 03 03:30:26 2009 +00001.3 @@ -32,6 +32,7 @@1.4 #include "sh4/sh4stat.h"1.5 #include "sh4/sh4mmio.h"1.6 #include "sh4/x86op.h"1.7 +#include "sh4/mmu.h"1.8 #include "clock.h"1.10 #define DEFAULT_BACKPATCH_SIZE 40961.11 @@ -177,6 +178,7 @@1.12 OP32(value);1.13 }1.15 +1.16 /**1.17 * Load an immediate 64-bit quantity (note: x86-64 only)1.18 */1.19 @@ -287,29 +289,22 @@1.20 #define UNDEF(ir)1.21 #define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )1.22 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }1.23 -#define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); call_func1_r32disp8(R_ECX, MEM_REGION_PTR(read_byte), addr_reg ); MEM_RESULT(value_reg)1.24 -#define MEM_READ_WORD( addr_reg, value_reg ) decode_address(addr_reg); call_func1_r32disp8(R_ECX, MEM_REGION_PTR(read_word), addr_reg ); MEM_RESULT(value_reg)1.25 -#define MEM_READ_LONG( addr_reg, value_reg ) decode_address(addr_reg); call_func1_r32disp8(R_ECX, MEM_REGION_PTR(read_long), addr_reg ); MEM_RESULT(value_reg)1.26 -#define MEM_WRITE_BYTE( addr_reg, value_reg ) decode_address(addr_reg); call_func2_r32disp8(R_ECX, MEM_REGION_PTR(write_byte), addr_reg, value_reg)1.27 -#define MEM_WRITE_WORD( addr_reg, value_reg ) decode_address(addr_reg); call_func2_r32disp8(R_ECX, MEM_REGION_PTR(write_word), addr_reg, value_reg)1.28 -#define MEM_WRITE_LONG( addr_reg, value_reg ) decode_address(addr_reg); call_func2_r32disp8(R_ECX, MEM_REGION_PTR(write_long), addr_reg, value_reg)1.29 -1.30 -#ifdef HAVE_FRAME_ADDRESS1.31 -/**1.32 - * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned1.33 - * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.1.34 +/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so1.35 + * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.1.36 */1.37 -#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1_exc(mmu_vma_to_phys_read, addr_reg, pc); MEM_RESULT(addr_reg); }1.38 -1.39 -/**1.40 - * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned1.41 - * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.1.42 - */1.43 -#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1_exc(mmu_vma_to_phys_write, addr_reg, pc); MEM_RESULT(addr_reg); }1.44 -#else1.45 -#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }1.46 -#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }1.47 -#endif1.48 +#define _CALL_READ(addr_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \1.49 + call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \1.50 + call_func1_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, pc); }1.51 +#define _CALL_WRITE(addr_reg, val_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \1.52 + call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \1.53 + call_func2_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); }1.54 +1.55 +#define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte); MEM_RESULT(value_reg)1.56 +#define MEM_READ_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_word); MEM_RESULT(value_reg)1.57 +#define MEM_READ_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_long); MEM_RESULT(value_reg)1.58 +#define MEM_WRITE_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_byte)1.59 +#define MEM_WRITE_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_word)1.60 +#define MEM_WRITE_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_long)1.62 #define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 2;1.64 @@ -328,7 +323,7 @@1.65 sh4_x86.branch_taken = FALSE;1.66 sh4_x86.backpatch_posn = 0;1.67 sh4_x86.block_start_pc = pc;1.68 - sh4_x86.tlb_on = IS_MMU_ENABLED();1.69 + sh4_x86.tlb_on = IS_TLB_ENABLED();1.70 sh4_x86.tstate = TSTATE_NONE;1.71 sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;1.72 sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;1.73 @@ -421,9 +416,7 @@1.74 :}1.75 ADD #imm, Rn {:1.76 COUNT_INST(I_ADDI);1.77 - load_reg( R_EAX, Rn );1.78 - ADD_imm8s_r32( imm, R_EAX );1.79 - store_reg( R_EAX, Rn );1.80 + ADD_imm8s_sh4r( imm, REG_OFFSET(r[Rn]) );1.81 sh4_x86.tstate = TSTATE_NONE;1.82 :}1.83 ADDC Rm, Rn {:1.84 @@ -465,9 +458,7 @@1.85 AND.B #imm, @(R0, GBR) {:1.86 COUNT_INST(I_ANDB);1.87 load_reg( R_EAX, 0 );1.88 - load_spreg( R_ECX, R_GBR );1.89 - ADD_r32_r32( R_ECX, R_EAX );1.90 - MMU_TRANSLATE_WRITE( R_EAX );1.91 + ADD_sh4r_r32( R_GBR, R_EAX );1.92 MOV_r32_esp8(R_EAX, 0);1.93 MEM_READ_BYTE( R_EAX, R_EDX );1.94 MOV_esp8_r32(0, R_EAX);1.95 @@ -656,32 +647,25 @@1.96 if( Rm == Rn ) {1.97 load_reg( R_EAX, Rm );1.98 check_ralign32( R_EAX );1.99 - MMU_TRANSLATE_READ( R_EAX );1.100 + MEM_READ_LONG( R_EAX, R_EAX );1.101 MOV_r32_esp8(R_EAX, 0);1.102 - load_reg( R_EAX, Rn );1.103 - ADD_imm8s_r32( 4, R_EAX );1.104 - MMU_TRANSLATE_READ( R_EAX );1.105 - ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );1.106 - // Note translate twice in case of page boundaries. Maybe worth1.107 - // adding a page-boundary check to skip the second translation1.108 + load_reg( R_EAX, Rm );1.109 + LEA_r32disp8_r32( R_EAX, 4, R_EAX );1.110 + MEM_READ_LONG( R_EAX, R_EAX );1.111 + ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );1.112 } else {1.113 load_reg( R_EAX, Rm );1.114 check_ralign32( R_EAX );1.115 - MMU_TRANSLATE_READ( R_EAX );1.116 + MEM_READ_LONG( R_EAX, R_EAX );1.117 MOV_r32_esp8( R_EAX, 0 );1.118 load_reg( R_EAX, Rn );1.119 check_ralign32( R_EAX );1.120 - MMU_TRANSLATE_READ( R_EAX );1.121 + MEM_READ_LONG( R_EAX, R_EAX );1.122 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );1.123 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.124 }1.125 - MEM_READ_LONG( R_EAX, R_EAX );1.126 - MOV_r32_esp8( R_EAX, 4 );1.127 - MOV_esp8_r32( 0, R_EAX );1.128 - MEM_READ_LONG( R_EAX, R_EAX );1.129 - MOV_esp8_r32( 4, R_ECX );1.130 -1.131 - IMUL_r32( R_ECX );1.132 +1.133 + IMUL_esp8( 0 );1.134 ADD_r32_sh4r( R_EAX, R_MACL );1.135 ADC_r32_sh4r( R_EDX, R_MACH );1.137 @@ -697,32 +681,26 @@1.138 if( Rm == Rn ) {1.139 load_reg( R_EAX, Rm );1.140 check_ralign16( R_EAX );1.141 - MMU_TRANSLATE_READ( R_EAX );1.142 + MEM_READ_WORD( R_EAX, R_EAX );1.143 MOV_r32_esp8( R_EAX, 0 );1.144 - load_reg( R_EAX, Rn );1.145 - ADD_imm8s_r32( 2, R_EAX );1.146 - MMU_TRANSLATE_READ( R_EAX );1.147 + load_reg( R_EAX, Rm );1.148 + LEA_r32disp8_r32( R_EAX, 2, R_EAX );1.149 + MEM_READ_WORD( R_EAX, R_EAX );1.150 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );1.151 // Note translate twice in case of page boundaries. Maybe worth1.152 // adding a page-boundary check to skip the second translation1.153 } else {1.154 load_reg( R_EAX, Rm );1.155 check_ralign16( R_EAX );1.156 - MMU_TRANSLATE_READ( R_EAX );1.157 + MEM_READ_WORD( R_EAX, R_EAX );1.158 MOV_r32_esp8( R_EAX, 0 );1.159 load_reg( R_EAX, Rn );1.160 check_ralign16( R_EAX );1.161 - MMU_TRANSLATE_READ( R_EAX );1.162 + MEM_READ_WORD( R_EAX, R_EAX );1.163 ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );1.164 ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );1.165 }1.166 - MEM_READ_WORD( R_EAX, R_EAX );1.167 - MOV_r32_esp8( R_EAX, 4 );1.168 - MOV_esp8_r32( 0, R_EAX );1.169 - MEM_READ_WORD( R_EAX, R_EAX );1.170 - MOV_esp8_r32( 4, R_ECX );1.171 -1.172 - IMUL_r32( R_ECX );1.173 + IMUL_esp8( 0 );1.174 load_spreg( R_ECX, R_S );1.175 TEST_r32_r32( R_ECX, R_ECX );1.176 JE_rel8( nosat );1.177 @@ -820,9 +798,7 @@1.178 OR.B #imm, @(R0, GBR) {:1.179 COUNT_INST(I_ORB);1.180 load_reg( R_EAX, 0 );1.181 - load_spreg( R_ECX, R_GBR );1.182 - ADD_r32_r32( R_ECX, R_EAX );1.183 - MMU_TRANSLATE_WRITE( R_EAX );1.184 + ADD_sh4r_r32( R_GBR, R_EAX );1.185 MOV_r32_esp8( R_EAX, 0 );1.186 MEM_READ_BYTE( R_EAX, R_EDX );1.187 MOV_esp8_r32( 0, R_EAX );1.188 @@ -1041,7 +1017,6 @@1.189 TAS.B @Rn {:1.190 COUNT_INST(I_TASB);1.191 load_reg( R_EAX, Rn );1.192 - MMU_TRANSLATE_WRITE( R_EAX );1.193 MOV_r32_esp8( R_EAX, 0 );1.194 MEM_READ_BYTE( R_EAX, R_EDX );1.195 TEST_r8_r8( R_DL, R_DL );1.196 @@ -1069,9 +1044,7 @@1.197 TST.B #imm, @(R0, GBR) {:1.198 COUNT_INST(I_TSTB);1.199 load_reg( R_EAX, 0);1.200 - load_reg( R_ECX, R_GBR);1.201 - ADD_r32_r32( R_ECX, R_EAX );1.202 - MMU_TRANSLATE_READ( R_EAX );1.203 + ADD_sh4r_r32( R_GBR, R_EAX );1.204 MEM_READ_BYTE( R_EAX, R_EAX );1.205 TEST_imm8_r8( imm, R_AL );1.206 SETE_t();1.207 @@ -1095,9 +1068,7 @@1.208 XOR.B #imm, @(R0, GBR) {:1.209 COUNT_INST(I_XORB);1.210 load_reg( R_EAX, 0 );1.211 - load_spreg( R_ECX, R_GBR );1.212 - ADD_r32_r32( R_ECX, R_EAX );1.213 - MMU_TRANSLATE_WRITE( R_EAX );1.214 + ADD_sh4r_r32( R_GBR, R_EAX );1.215 MOV_r32_esp8( R_EAX, 0 );1.216 MEM_READ_BYTE(R_EAX, R_EDX);1.217 MOV_esp8_r32( 0, R_EAX );1.218 @@ -1130,7 +1101,6 @@1.219 MOV.B Rm, @Rn {:1.220 COUNT_INST(I_MOVB);1.221 load_reg( R_EAX, Rn );1.222 - MMU_TRANSLATE_WRITE( R_EAX );1.223 load_reg( R_EDX, Rm );1.224 MEM_WRITE_BYTE( R_EAX, R_EDX );1.225 sh4_x86.tstate = TSTATE_NONE;1.226 @@ -1138,19 +1108,16 @@1.227 MOV.B Rm, @-Rn {:1.228 COUNT_INST(I_MOVB);1.229 load_reg( R_EAX, Rn );1.230 - ADD_imm8s_r32( -1, R_EAX );1.231 - MMU_TRANSLATE_WRITE( R_EAX );1.232 + LEA_r32disp8_r32( R_EAX, -1, R_EAX );1.233 load_reg( R_EDX, Rm );1.234 + MEM_WRITE_BYTE( R_EAX, R_EDX );1.235 ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );1.236 - MEM_WRITE_BYTE( R_EAX, R_EDX );1.237 sh4_x86.tstate = TSTATE_NONE;1.238 :}1.239 MOV.B Rm, @(R0, Rn) {:1.240 COUNT_INST(I_MOVB);1.241 load_reg( R_EAX, 0 );1.242 - load_reg( R_ECX, Rn );1.243 - ADD_r32_r32( R_ECX, R_EAX );1.244 - MMU_TRANSLATE_WRITE( R_EAX );1.245 + ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );1.246 load_reg( R_EDX, Rm );1.247 MEM_WRITE_BYTE( R_EAX, R_EDX );1.248 sh4_x86.tstate = TSTATE_NONE;1.249 @@ -1159,7 +1126,6 @@1.250 COUNT_INST(I_MOVB);1.251 load_spreg( R_EAX, R_GBR );1.252 ADD_imm32_r32( disp, R_EAX );1.253 - MMU_TRANSLATE_WRITE( R_EAX );1.254 load_reg( R_EDX, 0 );1.255 MEM_WRITE_BYTE( R_EAX, R_EDX );1.256 sh4_x86.tstate = TSTATE_NONE;1.257 @@ -1168,7 +1134,6 @@1.258 COUNT_INST(I_MOVB);1.259 load_reg( R_EAX, Rn );1.260 ADD_imm32_r32( disp, R_EAX );1.261 - MMU_TRANSLATE_WRITE( R_EAX );1.262 load_reg( R_EDX, 0 );1.263 MEM_WRITE_BYTE( R_EAX, R_EDX );1.264 sh4_x86.tstate = TSTATE_NONE;1.265 @@ -1176,7 +1141,6 @@1.266 MOV.B @Rm, Rn {:1.267 COUNT_INST(I_MOVB);1.268 load_reg( R_EAX, Rm );1.269 - MMU_TRANSLATE_READ( R_EAX );1.270 MEM_READ_BYTE( R_EAX, R_EAX );1.271 store_reg( R_EAX, Rn );1.272 sh4_x86.tstate = TSTATE_NONE;1.273 @@ -1184,18 +1148,17 @@1.274 MOV.B @Rm+, Rn {:1.275 COUNT_INST(I_MOVB);1.276 load_reg( R_EAX, Rm );1.277 - MMU_TRANSLATE_READ( R_EAX );1.278 - ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );1.279 MEM_READ_BYTE( R_EAX, R_EAX );1.280 + if( Rm != Rn ) {1.281 + ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );1.282 + }1.283 store_reg( R_EAX, Rn );1.284 sh4_x86.tstate = TSTATE_NONE;1.285 :}1.286 MOV.B @(R0, Rm), Rn {:1.287 COUNT_INST(I_MOVB);1.288 load_reg( R_EAX, 0 );1.289 - load_reg( R_ECX, Rm );1.290 - ADD_r32_r32( R_ECX, R_EAX );1.291 - MMU_TRANSLATE_READ( R_EAX )1.292 + ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );1.293 MEM_READ_BYTE( R_EAX, R_EAX );1.294 store_reg( R_EAX, Rn );1.295 sh4_x86.tstate = TSTATE_NONE;1.296 @@ -1204,7 +1167,6 @@1.297 COUNT_INST(I_MOVB);1.298 load_spreg( R_EAX, R_GBR );1.299 ADD_imm32_r32( disp, R_EAX );1.300 - MMU_TRANSLATE_READ( R_EAX );1.301 MEM_READ_BYTE( R_EAX, R_EAX );1.302 store_reg( R_EAX, 0 );1.303 sh4_x86.tstate = TSTATE_NONE;1.304 @@ -1213,7 +1175,6 @@1.305 COUNT_INST(I_MOVB);1.306 load_reg( R_EAX, Rm );1.307 ADD_imm32_r32( disp, R_EAX );1.308 - MMU_TRANSLATE_READ( R_EAX );1.309 MEM_READ_BYTE( R_EAX, R_EAX );1.310 store_reg( R_EAX, 0 );1.311 sh4_x86.tstate = TSTATE_NONE;1.312 @@ -1231,7 +1192,6 @@1.313 MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );1.314 JMP_rel8(end);1.315 JMP_TARGET(notsq);1.316 - MMU_TRANSLATE_WRITE( R_EAX );1.317 load_reg( R_EDX, Rm );1.318 MEM_WRITE_LONG( R_EAX, R_EDX );1.319 JMP_TARGET(end);1.320 @@ -1242,19 +1202,16 @@1.321 load_reg( R_EAX, Rn );1.322 ADD_imm8s_r32( -4, R_EAX );1.323 check_walign32( R_EAX );1.324 - MMU_TRANSLATE_WRITE( R_EAX );1.325 load_reg( R_EDX, Rm );1.326 + MEM_WRITE_LONG( R_EAX, R_EDX );1.327 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.328 - MEM_WRITE_LONG( R_EAX, R_EDX );1.329 sh4_x86.tstate = TSTATE_NONE;1.330 :}1.331 MOV.L Rm, @(R0, Rn) {:1.332 COUNT_INST(I_MOVL);1.333 load_reg( R_EAX, 0 );1.334 - load_reg( R_ECX, Rn );1.335 - ADD_r32_r32( R_ECX, R_EAX );1.336 + ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );1.337 check_walign32( R_EAX );1.338 - MMU_TRANSLATE_WRITE( R_EAX );1.339 load_reg( R_EDX, Rm );1.340 MEM_WRITE_LONG( R_EAX, R_EDX );1.341 sh4_x86.tstate = TSTATE_NONE;1.342 @@ -1264,7 +1221,6 @@1.343 load_spreg( R_EAX, R_GBR );1.344 ADD_imm32_r32( disp, R_EAX );1.345 check_walign32( R_EAX );1.346 - MMU_TRANSLATE_WRITE( R_EAX );1.347 load_reg( R_EDX, 0 );1.348 MEM_WRITE_LONG( R_EAX, R_EDX );1.349 sh4_x86.tstate = TSTATE_NONE;1.350 @@ -1283,7 +1239,6 @@1.351 MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );1.352 JMP_rel8(end);1.353 JMP_TARGET(notsq);1.354 - MMU_TRANSLATE_WRITE( R_EAX );1.355 load_reg( R_EDX, Rm );1.356 MEM_WRITE_LONG( R_EAX, R_EDX );1.357 JMP_TARGET(end);1.358 @@ -1293,7 +1248,6 @@1.359 COUNT_INST(I_MOVL);1.360 load_reg( R_EAX, Rm );1.361 check_ralign32( R_EAX );1.362 - MMU_TRANSLATE_READ( R_EAX );1.363 MEM_READ_LONG( R_EAX, R_EAX );1.364 store_reg( R_EAX, Rn );1.365 sh4_x86.tstate = TSTATE_NONE;1.366 @@ -1302,19 +1256,18 @@1.367 COUNT_INST(I_MOVL);1.368 load_reg( R_EAX, Rm );1.369 check_ralign32( R_EAX );1.370 - MMU_TRANSLATE_READ( R_EAX );1.371 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.372 MEM_READ_LONG( R_EAX, R_EAX );1.373 + if( Rm != Rn ) {1.374 + ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.375 + }1.376 store_reg( R_EAX, Rn );1.377 sh4_x86.tstate = TSTATE_NONE;1.378 :}1.379 MOV.L @(R0, Rm), Rn {:1.380 COUNT_INST(I_MOVL);1.381 load_reg( R_EAX, 0 );1.382 - load_reg( R_ECX, Rm );1.383 - ADD_r32_r32( R_ECX, R_EAX );1.384 + ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );1.385 check_ralign32( R_EAX );1.386 - MMU_TRANSLATE_READ( R_EAX );1.387 MEM_READ_LONG( R_EAX, R_EAX );1.388 store_reg( R_EAX, Rn );1.389 sh4_x86.tstate = TSTATE_NONE;1.390 @@ -1324,7 +1277,6 @@1.391 load_spreg( R_EAX, R_GBR );1.392 ADD_imm32_r32( disp, R_EAX );1.393 check_ralign32( R_EAX );1.394 - MMU_TRANSLATE_READ( R_EAX );1.395 MEM_READ_LONG( R_EAX, R_EAX );1.396 store_reg( R_EAX, 0 );1.397 sh4_x86.tstate = TSTATE_NONE;1.398 @@ -1353,7 +1305,6 @@1.399 // but we can safely assume that the low bits are the same.1.400 load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );1.401 ADD_sh4r_r32( R_PC, R_EAX );1.402 - MMU_TRANSLATE_READ( R_EAX );1.403 MEM_READ_LONG( R_EAX, R_EAX );1.404 sh4_x86.tstate = TSTATE_NONE;1.405 }1.406 @@ -1365,7 +1316,6 @@1.407 load_reg( R_EAX, Rm );1.408 ADD_imm8s_r32( disp, R_EAX );1.409 check_ralign32( R_EAX );1.410 - MMU_TRANSLATE_READ( R_EAX );1.411 MEM_READ_LONG( R_EAX, R_EAX );1.412 store_reg( R_EAX, Rn );1.413 sh4_x86.tstate = TSTATE_NONE;1.414 @@ -1374,7 +1324,6 @@1.415 COUNT_INST(I_MOVW);1.416 load_reg( R_EAX, Rn );1.417 check_walign16( R_EAX );1.418 - MMU_TRANSLATE_WRITE( R_EAX )1.419 load_reg( R_EDX, Rm );1.420 MEM_WRITE_WORD( R_EAX, R_EDX );1.421 sh4_x86.tstate = TSTATE_NONE;1.422 @@ -1382,21 +1331,18 @@1.423 MOV.W Rm, @-Rn {:1.424 COUNT_INST(I_MOVW);1.425 load_reg( R_EAX, Rn );1.426 - ADD_imm8s_r32( -2, R_EAX );1.427 check_walign16( R_EAX );1.428 - MMU_TRANSLATE_WRITE( R_EAX );1.429 + LEA_r32disp8_r32( R_EAX, -2, R_EAX );1.430 load_reg( R_EDX, Rm );1.431 + MEM_WRITE_WORD( R_EAX, R_EDX );1.432 ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );1.433 - MEM_WRITE_WORD( R_EAX, R_EDX );1.434 sh4_x86.tstate = TSTATE_NONE;1.435 :}1.436 MOV.W Rm, @(R0, Rn) {:1.437 COUNT_INST(I_MOVW);1.438 load_reg( R_EAX, 0 );1.439 - load_reg( R_ECX, Rn );1.440 - ADD_r32_r32( R_ECX, R_EAX );1.441 + ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );1.442 check_walign16( R_EAX );1.443 - MMU_TRANSLATE_WRITE( R_EAX );1.444 load_reg( R_EDX, Rm );1.445 MEM_WRITE_WORD( R_EAX, R_EDX );1.446 sh4_x86.tstate = TSTATE_NONE;1.447 @@ -1406,7 +1352,6 @@1.448 load_spreg( R_EAX, R_GBR );1.449 ADD_imm32_r32( disp, R_EAX );1.450 check_walign16( R_EAX );1.451 - MMU_TRANSLATE_WRITE( R_EAX );1.452 load_reg( R_EDX, 0 );1.453 MEM_WRITE_WORD( R_EAX, R_EDX );1.454 sh4_x86.tstate = TSTATE_NONE;1.455 @@ -1416,7 +1361,6 @@1.456 load_reg( R_EAX, Rn );1.457 ADD_imm32_r32( disp, R_EAX );1.458 check_walign16( R_EAX );1.459 - MMU_TRANSLATE_WRITE( R_EAX );1.460 load_reg( R_EDX, 0 );1.461 MEM_WRITE_WORD( R_EAX, R_EDX );1.462 sh4_x86.tstate = TSTATE_NONE;1.463 @@ -1425,7 +1369,6 @@1.464 COUNT_INST(I_MOVW);1.465 load_reg( R_EAX, Rm );1.466 check_ralign16( R_EAX );1.467 - MMU_TRANSLATE_READ( R_EAX );1.468 MEM_READ_WORD( R_EAX, R_EAX );1.469 store_reg( R_EAX, Rn );1.470 sh4_x86.tstate = TSTATE_NONE;1.471 @@ -1434,19 +1377,18 @@1.472 COUNT_INST(I_MOVW);1.473 load_reg( R_EAX, Rm );1.474 check_ralign16( R_EAX );1.475 - MMU_TRANSLATE_READ( R_EAX );1.476 - ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );1.477 MEM_READ_WORD( R_EAX, R_EAX );1.478 + if( Rm != Rn ) {1.479 + ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );1.480 + }1.481 store_reg( R_EAX, Rn );1.482 sh4_x86.tstate = TSTATE_NONE;1.483 :}1.484 MOV.W @(R0, Rm), Rn {:1.485 COUNT_INST(I_MOVW);1.486 load_reg( R_EAX, 0 );1.487 - load_reg( R_ECX, Rm );1.488 - ADD_r32_r32( R_ECX, R_EAX );1.489 + ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );1.490 check_ralign16( R_EAX );1.491 - MMU_TRANSLATE_READ( R_EAX );1.492 MEM_READ_WORD( R_EAX, R_EAX );1.493 store_reg( R_EAX, Rn );1.494 sh4_x86.tstate = TSTATE_NONE;1.495 @@ -1456,7 +1398,6 @@1.496 load_spreg( R_EAX, R_GBR );1.497 ADD_imm32_r32( disp, R_EAX );1.498 check_ralign16( R_EAX );1.499 - MMU_TRANSLATE_READ( R_EAX );1.500 MEM_READ_WORD( R_EAX, R_EAX );1.501 store_reg( R_EAX, 0 );1.502 sh4_x86.tstate = TSTATE_NONE;1.503 @@ -1475,7 +1416,6 @@1.504 } else {1.505 load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );1.506 ADD_sh4r_r32( R_PC, R_EAX );1.507 - MMU_TRANSLATE_READ( R_EAX );1.508 MEM_READ_WORD( R_EAX, R_EAX );1.509 sh4_x86.tstate = TSTATE_NONE;1.510 }1.511 @@ -1487,7 +1427,6 @@1.512 load_reg( R_EAX, Rm );1.513 ADD_imm32_r32( disp, R_EAX );1.514 check_ralign16( R_EAX );1.515 - MMU_TRANSLATE_READ( R_EAX );1.516 MEM_READ_WORD( R_EAX, R_EAX );1.517 store_reg( R_EAX, 0 );1.518 sh4_x86.tstate = TSTATE_NONE;1.519 @@ -1507,7 +1446,6 @@1.520 COUNT_INST(I_MOVCA);1.521 load_reg( R_EAX, Rn );1.522 check_walign32( R_EAX );1.523 - MMU_TRANSLATE_WRITE( R_EAX );1.524 load_reg( R_EDX, 0 );1.525 MEM_WRITE_LONG( R_EAX, R_EDX );1.526 sh4_x86.tstate = TSTATE_NONE;1.527 @@ -1857,13 +1795,14 @@1.528 load_reg( R_EAX, Rn );1.529 if( sh4_x86.double_size ) {1.530 check_walign64( R_EAX );1.531 - MMU_TRANSLATE_WRITE( R_EAX );1.532 load_dr0( R_EDX, FRm );1.533 - load_dr1( R_ECX, FRm );1.534 - MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );1.535 + MEM_WRITE_LONG( R_EAX, R_EDX );1.536 + load_reg( R_EAX, Rn );1.537 + LEA_r32disp8_r32( R_EAX, 4, R_EAX );1.538 + load_dr1( R_EDX, FRm );1.539 + MEM_WRITE_LONG( R_EAX, R_EDX );1.540 } else {1.541 check_walign32( R_EAX );1.542 - MMU_TRANSLATE_WRITE( R_EAX );1.543 load_fr( R_EDX, FRm );1.544 MEM_WRITE_LONG( R_EAX, R_EDX );1.545 }1.546 @@ -1875,13 +1814,14 @@1.547 load_reg( R_EAX, Rm );1.548 if( sh4_x86.double_size ) {1.549 check_ralign64( R_EAX );1.550 - MMU_TRANSLATE_READ( R_EAX );1.551 - MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );1.552 - store_dr0( R_EDX, FRn );1.553 - store_dr1( R_EAX, FRn );1.554 + MEM_READ_LONG( R_EAX, R_EAX );1.555 + store_dr0( R_EAX, FRn );1.556 + load_reg( R_EAX, Rm );1.557 + LEA_r32disp8_r32( R_EAX, 4, R_EAX );1.558 + MEM_READ_LONG( R_EAX, R_EAX );1.559 + store_dr1( R_EAX, FRn );1.560 } else {1.561 check_ralign32( R_EAX );1.562 - MMU_TRANSLATE_READ( R_EAX );1.563 MEM_READ_LONG( R_EAX, R_EAX );1.564 store_fr( R_EAX, FRn );1.565 }1.566 @@ -1893,19 +1833,20 @@1.567 load_reg( R_EAX, Rn );1.568 if( sh4_x86.double_size ) {1.569 check_walign64( R_EAX );1.570 - ADD_imm8s_r32(-8,R_EAX);1.571 - MMU_TRANSLATE_WRITE( R_EAX );1.572 + LEA_r32disp8_r32( R_EAX, -8, R_EAX );1.573 load_dr0( R_EDX, FRm );1.574 - load_dr1( R_ECX, FRm );1.575 + MEM_WRITE_LONG( R_EAX, R_EDX );1.576 + load_reg( R_EAX, Rn );1.577 + LEA_r32disp8_r32( R_EAX, -4, R_EAX );1.578 + load_dr1( R_EDX, FRm );1.579 + MEM_WRITE_LONG( R_EAX, R_EDX );1.580 ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));1.581 - MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );1.582 } else {1.583 check_walign32( R_EAX );1.584 - ADD_imm8s_r32( -4, R_EAX );1.585 - MMU_TRANSLATE_WRITE( R_EAX );1.586 + LEA_r32disp8_r32( R_EAX, -4, R_EAX );1.587 load_fr( R_EDX, FRm );1.588 + MEM_WRITE_LONG( R_EAX, R_EDX );1.589 ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));1.590 - MEM_WRITE_LONG( R_EAX, R_EDX );1.591 }1.592 sh4_x86.tstate = TSTATE_NONE;1.593 :}1.594 @@ -1915,17 +1856,18 @@1.595 load_reg( R_EAX, Rm );1.596 if( sh4_x86.double_size ) {1.597 check_ralign64( R_EAX );1.598 - MMU_TRANSLATE_READ( R_EAX );1.599 + MEM_READ_LONG( R_EAX, R_EAX );1.600 + store_dr0( R_EAX, FRn );1.601 + load_reg( R_EAX, Rm );1.602 + LEA_r32disp8_r32( R_EAX, 4, R_EAX );1.603 + MEM_READ_LONG( R_EAX, R_EAX );1.604 + store_dr1( R_EAX, FRn );1.605 ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );1.606 - MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );1.607 - store_dr0( R_EDX, FRn );1.608 - store_dr1( R_EAX, FRn );1.609 } else {1.610 check_ralign32( R_EAX );1.611 - MMU_TRANSLATE_READ( R_EAX );1.612 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.613 MEM_READ_LONG( R_EAX, R_EAX );1.614 store_fr( R_EAX, FRn );1.615 + ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.616 }1.617 sh4_x86.tstate = TSTATE_NONE;1.618 :}1.619 @@ -1936,13 +1878,15 @@1.620 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );1.621 if( sh4_x86.double_size ) {1.622 check_walign64( R_EAX );1.623 - MMU_TRANSLATE_WRITE( R_EAX );1.624 load_dr0( R_EDX, FRm );1.625 - load_dr1( R_ECX, FRm );1.626 - MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );1.627 + MEM_WRITE_LONG( R_EAX, R_EDX );1.628 + load_reg( R_EAX, Rn );1.629 + ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );1.630 + LEA_r32disp8_r32( R_EAX, 4, R_EAX );1.631 + load_dr1( R_EDX, FRm );1.632 + MEM_WRITE_LONG( R_EAX, R_EDX );1.633 } else {1.634 check_walign32( R_EAX );1.635 - MMU_TRANSLATE_WRITE( R_EAX );1.636 load_fr( R_EDX, FRm );1.637 MEM_WRITE_LONG( R_EAX, R_EDX ); // 121.638 }1.639 @@ -1955,13 +1899,15 @@1.640 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );1.641 if( sh4_x86.double_size ) {1.642 check_ralign64( R_EAX );1.643 - MMU_TRANSLATE_READ( R_EAX );1.644 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );1.645 - store_dr0( R_ECX, FRn );1.646 + MEM_READ_LONG( R_EAX, R_EAX );1.647 + store_dr0( R_EAX, FRn );1.648 + load_reg( R_EAX, Rm );1.649 + ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );1.650 + LEA_r32disp8_r32( R_EAX, 4, R_EAX );1.651 + MEM_READ_LONG( R_EAX, R_EAX );1.652 store_dr1( R_EAX, FRn );1.653 } else {1.654 check_ralign32( R_EAX );1.655 - MMU_TRANSLATE_READ( R_EAX );1.656 MEM_READ_LONG( R_EAX, R_EAX );1.657 store_fr( R_EAX, FRn );1.658 }1.659 @@ -2374,9 +2320,8 @@1.660 COUNT_INST(I_LDCM);1.661 load_reg( R_EAX, Rm );1.662 check_ralign32( R_EAX );1.663 - MMU_TRANSLATE_READ( R_EAX );1.664 + MEM_READ_LONG( R_EAX, R_EAX );1.665 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.666 - MEM_READ_LONG( R_EAX, R_EAX );1.667 store_spreg( R_EAX, R_GBR );1.668 sh4_x86.tstate = TSTATE_NONE;1.669 :}1.670 @@ -2388,9 +2333,8 @@1.671 check_priv();1.672 load_reg( R_EAX, Rm );1.673 check_ralign32( R_EAX );1.674 - MMU_TRANSLATE_READ( R_EAX );1.675 + MEM_READ_LONG( R_EAX, R_EAX );1.676 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.677 - MEM_READ_LONG( R_EAX, R_EAX );1.678 call_func1( sh4_write_sr, R_EAX );1.679 sh4_x86.fpuen_checked = FALSE;1.680 sh4_x86.tstate = TSTATE_NONE;1.681 @@ -2402,9 +2346,8 @@1.682 check_priv();1.683 load_reg( R_EAX, Rm );1.684 check_ralign32( R_EAX );1.685 - MMU_TRANSLATE_READ( R_EAX );1.686 + MEM_READ_LONG( R_EAX, R_EAX );1.687 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.688 - MEM_READ_LONG( R_EAX, R_EAX );1.689 store_spreg( R_EAX, R_VBR );1.690 sh4_x86.tstate = TSTATE_NONE;1.691 :}1.692 @@ -2413,9 +2356,8 @@1.693 check_priv();1.694 load_reg( R_EAX, Rm );1.695 check_ralign32( R_EAX );1.696 - MMU_TRANSLATE_READ( R_EAX );1.697 + MEM_READ_LONG( R_EAX, R_EAX );1.698 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.699 - MEM_READ_LONG( R_EAX, R_EAX );1.700 store_spreg( R_EAX, R_SSR );1.701 sh4_x86.tstate = TSTATE_NONE;1.702 :}1.703 @@ -2424,9 +2366,8 @@1.704 check_priv();1.705 load_reg( R_EAX, Rm );1.706 check_ralign32( R_EAX );1.707 - MMU_TRANSLATE_READ( R_EAX );1.708 + MEM_READ_LONG( R_EAX, R_EAX );1.709 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.710 - MEM_READ_LONG( R_EAX, R_EAX );1.711 store_spreg( R_EAX, R_SGR );1.712 sh4_x86.tstate = TSTATE_NONE;1.713 :}1.714 @@ -2435,9 +2376,8 @@1.715 check_priv();1.716 load_reg( R_EAX, Rm );1.717 check_ralign32( R_EAX );1.718 - MMU_TRANSLATE_READ( R_EAX );1.719 + MEM_READ_LONG( R_EAX, R_EAX );1.720 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.721 - MEM_READ_LONG( R_EAX, R_EAX );1.722 store_spreg( R_EAX, R_SPC );1.723 sh4_x86.tstate = TSTATE_NONE;1.724 :}1.725 @@ -2446,9 +2386,8 @@1.726 check_priv();1.727 load_reg( R_EAX, Rm );1.728 check_ralign32( R_EAX );1.729 - MMU_TRANSLATE_READ( R_EAX );1.730 + MEM_READ_LONG( R_EAX, R_EAX );1.731 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.732 - MEM_READ_LONG( R_EAX, R_EAX );1.733 store_spreg( R_EAX, R_DBR );1.734 sh4_x86.tstate = TSTATE_NONE;1.735 :}1.736 @@ -2457,9 +2396,8 @@1.737 check_priv();1.738 load_reg( R_EAX, Rm );1.739 check_ralign32( R_EAX );1.740 - MMU_TRANSLATE_READ( R_EAX );1.741 + MEM_READ_LONG( R_EAX, R_EAX );1.742 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.743 - MEM_READ_LONG( R_EAX, R_EAX );1.744 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );1.745 sh4_x86.tstate = TSTATE_NONE;1.746 :}1.747 @@ -2476,9 +2414,8 @@1.748 check_fpuen();1.749 load_reg( R_EAX, Rm );1.750 check_ralign32( R_EAX );1.751 - MMU_TRANSLATE_READ( R_EAX );1.752 + MEM_READ_LONG( R_EAX, R_EAX );1.753 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.754 - MEM_READ_LONG( R_EAX, R_EAX );1.755 call_func1( sh4_write_fpscr, R_EAX );1.756 sh4_x86.tstate = TSTATE_NONE;1.757 return 2;1.758 @@ -2494,9 +2431,8 @@1.759 check_fpuen();1.760 load_reg( R_EAX, Rm );1.761 check_ralign32( R_EAX );1.762 - MMU_TRANSLATE_READ( R_EAX );1.763 + MEM_READ_LONG( R_EAX, R_EAX );1.764 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.765 - MEM_READ_LONG( R_EAX, R_EAX );1.766 store_spreg( R_EAX, R_FPUL );1.767 sh4_x86.tstate = TSTATE_NONE;1.768 :}1.769 @@ -2509,9 +2445,8 @@1.770 COUNT_INST(I_LDSM);1.771 load_reg( R_EAX, Rm );1.772 check_ralign32( R_EAX );1.773 - MMU_TRANSLATE_READ( R_EAX );1.774 + MEM_READ_LONG( R_EAX, R_EAX );1.775 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.776 - MEM_READ_LONG( R_EAX, R_EAX );1.777 store_spreg( R_EAX, R_MACH );1.778 sh4_x86.tstate = TSTATE_NONE;1.779 :}1.780 @@ -2524,9 +2459,8 @@1.781 COUNT_INST(I_LDSM);1.782 load_reg( R_EAX, Rm );1.783 check_ralign32( R_EAX );1.784 - MMU_TRANSLATE_READ( R_EAX );1.785 + MEM_READ_LONG( R_EAX, R_EAX );1.786 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.787 - MEM_READ_LONG( R_EAX, R_EAX );1.788 store_spreg( R_EAX, R_MACL );1.789 sh4_x86.tstate = TSTATE_NONE;1.790 :}1.791 @@ -2539,9 +2473,8 @@1.792 COUNT_INST(I_LDSM);1.793 load_reg( R_EAX, Rm );1.794 check_ralign32( R_EAX );1.795 - MMU_TRANSLATE_READ( R_EAX );1.796 + MEM_READ_LONG( R_EAX, R_EAX );1.797 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );1.798 - MEM_READ_LONG( R_EAX, R_EAX );1.799 store_spreg( R_EAX, R_PR );1.800 sh4_x86.tstate = TSTATE_NONE;1.801 :}1.802 @@ -2641,16 +2574,13 @@1.803 STC.L SR, @-Rn {:1.804 COUNT_INST(I_STCSRM);1.805 check_priv();1.806 + call_func0( sh4_read_sr );1.807 + MOV_r32_r32( R_EAX, R_EDX );1.808 load_reg( R_EAX, Rn );1.809 check_walign32( R_EAX );1.810 - ADD_imm8s_r32( -4, R_EAX );1.811 - MMU_TRANSLATE_WRITE( R_EAX );1.812 - MOV_r32_esp8( R_EAX, 0 );1.813 - call_func0( sh4_read_sr );1.814 - MOV_r32_r32( R_EAX, R_EDX );1.815 - MOV_esp8_r32( 0, R_EAX );1.816 + LEA_r32disp8_r32( R_EAX, -4, R_EAX );1.817 + MEM_WRITE_LONG( R_EAX, R_EDX );1.818 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.819 - MEM_WRITE_LONG( R_EAX, R_EDX );1.820 sh4_x86.tstate = TSTATE_NONE;1.821 :}1.822 STC.L VBR, @-Rn {:1.823 @@ -2659,10 +2589,9 @@1.824 load_reg( R_EAX, Rn );1.825 check_walign32( R_EAX );1.826 ADD_imm8s_r32( -4, R_EAX );1.827 - MMU_TRANSLATE_WRITE( R_EAX );1.828 load_spreg( R_EDX, R_VBR );1.829 + MEM_WRITE_LONG( R_EAX, R_EDX );1.830 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.831 - MEM_WRITE_LONG( R_EAX, R_EDX );1.832 sh4_x86.tstate = TSTATE_NONE;1.833 :}1.834 STC.L SSR, @-Rn {:1.835 @@ -2671,10 +2600,9 @@1.836 load_reg( R_EAX, Rn );1.837 check_walign32( R_EAX );1.838 ADD_imm8s_r32( -4, R_EAX );1.839 - MMU_TRANSLATE_WRITE( R_EAX );1.840 load_spreg( R_EDX, R_SSR );1.841 + MEM_WRITE_LONG( R_EAX, R_EDX );1.842 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.843 - MEM_WRITE_LONG( R_EAX, R_EDX );1.844 sh4_x86.tstate = TSTATE_NONE;1.845 :}1.846 STC.L SPC, @-Rn {:1.847 @@ -2683,10 +2611,9 @@1.848 load_reg( R_EAX, Rn );1.849 check_walign32( R_EAX );1.850 ADD_imm8s_r32( -4, R_EAX );1.851 - MMU_TRANSLATE_WRITE( R_EAX );1.852 load_spreg( R_EDX, R_SPC );1.853 + MEM_WRITE_LONG( R_EAX, R_EDX );1.854 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.855 - MEM_WRITE_LONG( R_EAX, R_EDX );1.856 sh4_x86.tstate = TSTATE_NONE;1.857 :}1.858 STC.L SGR, @-Rn {:1.859 @@ -2695,10 +2622,9 @@1.860 load_reg( R_EAX, Rn );1.861 check_walign32( R_EAX );1.862 ADD_imm8s_r32( -4, R_EAX );1.863 - MMU_TRANSLATE_WRITE( R_EAX );1.864 load_spreg( R_EDX, R_SGR );1.865 + MEM_WRITE_LONG( R_EAX, R_EDX );1.866 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.867 - MEM_WRITE_LONG( R_EAX, R_EDX );1.868 sh4_x86.tstate = TSTATE_NONE;1.869 :}1.870 STC.L DBR, @-Rn {:1.871 @@ -2707,10 +2633,9 @@1.872 load_reg( R_EAX, Rn );1.873 check_walign32( R_EAX );1.874 ADD_imm8s_r32( -4, R_EAX );1.875 - MMU_TRANSLATE_WRITE( R_EAX );1.876 load_spreg( R_EDX, R_DBR );1.877 + MEM_WRITE_LONG( R_EAX, R_EDX );1.878 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.879 - MEM_WRITE_LONG( R_EAX, R_EDX );1.880 sh4_x86.tstate = TSTATE_NONE;1.881 :}1.882 STC.L Rm_BANK, @-Rn {:1.883 @@ -2719,10 +2644,9 @@1.884 load_reg( R_EAX, Rn );1.885 check_walign32( R_EAX );1.886 ADD_imm8s_r32( -4, R_EAX );1.887 - MMU_TRANSLATE_WRITE( R_EAX );1.888 load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );1.889 + MEM_WRITE_LONG( R_EAX, R_EDX );1.890 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.891 - MEM_WRITE_LONG( R_EAX, R_EDX );1.892 sh4_x86.tstate = TSTATE_NONE;1.893 :}1.894 STC.L GBR, @-Rn {:1.895 @@ -2730,10 +2654,9 @@1.896 load_reg( R_EAX, Rn );1.897 check_walign32( R_EAX );1.898 ADD_imm8s_r32( -4, R_EAX );1.899 - MMU_TRANSLATE_WRITE( R_EAX );1.900 load_spreg( R_EDX, R_GBR );1.901 + MEM_WRITE_LONG( R_EAX, R_EDX );1.902 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.903 - MEM_WRITE_LONG( R_EAX, R_EDX );1.904 sh4_x86.tstate = TSTATE_NONE;1.905 :}1.906 STS FPSCR, Rn {:1.907 @@ -2748,10 +2671,9 @@1.908 load_reg( R_EAX, Rn );1.909 check_walign32( R_EAX );1.910 ADD_imm8s_r32( -4, R_EAX );1.911 - MMU_TRANSLATE_WRITE( R_EAX );1.912 load_spreg( R_EDX, R_FPSCR );1.913 + MEM_WRITE_LONG( R_EAX, R_EDX );1.914 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.915 - MEM_WRITE_LONG( R_EAX, R_EDX );1.916 sh4_x86.tstate = TSTATE_NONE;1.917 :}1.918 STS FPUL, Rn {:1.919 @@ -2766,10 +2688,9 @@1.920 load_reg( R_EAX, Rn );1.921 check_walign32( R_EAX );1.922 ADD_imm8s_r32( -4, R_EAX );1.923 - MMU_TRANSLATE_WRITE( R_EAX );1.924 load_spreg( R_EDX, R_FPUL );1.925 + MEM_WRITE_LONG( R_EAX, R_EDX );1.926 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.927 - MEM_WRITE_LONG( R_EAX, R_EDX );1.928 sh4_x86.tstate = TSTATE_NONE;1.929 :}1.930 STS MACH, Rn {:1.931 @@ -2782,10 +2703,9 @@1.932 load_reg( R_EAX, Rn );1.933 check_walign32( R_EAX );1.934 ADD_imm8s_r32( -4, R_EAX );1.935 - MMU_TRANSLATE_WRITE( R_EAX );1.936 load_spreg( R_EDX, R_MACH );1.937 + MEM_WRITE_LONG( R_EAX, R_EDX );1.938 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.939 - MEM_WRITE_LONG( R_EAX, R_EDX );1.940 sh4_x86.tstate = TSTATE_NONE;1.941 :}1.942 STS MACL, Rn {:1.943 @@ -2798,10 +2718,9 @@1.944 load_reg( R_EAX, Rn );1.945 check_walign32( R_EAX );1.946 ADD_imm8s_r32( -4, R_EAX );1.947 - MMU_TRANSLATE_WRITE( R_EAX );1.948 load_spreg( R_EDX, R_MACL );1.949 + MEM_WRITE_LONG( R_EAX, R_EDX );1.950 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.951 - MEM_WRITE_LONG( R_EAX, R_EDX );1.952 sh4_x86.tstate = TSTATE_NONE;1.953 :}1.954 STS PR, Rn {:1.955 @@ -2814,10 +2733,9 @@1.956 load_reg( R_EAX, Rn );1.957 check_walign32( R_EAX );1.958 ADD_imm8s_r32( -4, R_EAX );1.959 - MMU_TRANSLATE_WRITE( R_EAX );1.960 load_spreg( R_EDX, R_PR );1.961 + MEM_WRITE_LONG( R_EAX, R_EDX );1.962 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );1.963 - MEM_WRITE_LONG( R_EAX, R_EDX );1.964 sh4_x86.tstate = TSTATE_NONE;1.965 :}
.