filename | test/interrupt.s |
changeset | 228:70adc8ffa8d1 |
next | 233:f8333b94f503 |
author | nkeynes |
date | Mon Sep 25 11:13:56 2006 +0000 (17 years ago) |
permissions | -rw-r--r-- |
last change | Commit BF tests and initial exception handler |
file | annotate | diff | log | raw |
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +00001.2 +++ b/test/interrupt.s Mon Sep 25 11:13:56 2006 +00001.3 @@ -0,0 +1,247 @@1.4 +.section .text1.5 +.include "sh4/inc.s"1.6 +1.7 +! expect_interrupt( int intevt )1.8 +.global _expect_interrupt1.9 +_expect_interrupt:1.10 + stc sr, r3 ! Mask off interrupts1.11 + mov.l bl_mask, r01.12 + or r3, r01.13 + ldc r0, sr1.14 + mova expected_intevt, r01.15 + mov.l r4, @r01.16 + xor r1, r11.17 + mova expected_expevt, r01.18 + mov.l r1, @r01.19 + mova _interrupt_count, r01.20 + mov.l r1, @r01.21 + mova _interrupt_pc, r01.22 + mov.l r1, @r01.23 + ldc r3, sr ! Restore old SR state1.24 + rts1.25 + nop1.26 +1.27 + .global _expect_exception1.28 +_expect_exception:1.29 + stc sr, r3 ! Mask off interrupts1.30 + mov.l bl_mask, r01.31 + or r3, r01.32 + ldc r0, sr1.33 + mova expected_expevt, r01.34 + mov.l r4, @r01.35 + xor r1, r11.36 + mova expected_intevt, r01.37 + mov.l r1, @r01.38 + mova _interrupt_count, r01.39 + mov.l r1, @r01.40 + mova _interrupt_pc, r01.41 + mov.l r1, @r01.42 + ldc r3, sr ! Restore old SR state1.43 + rts1.44 + nop1.45 +1.46 + .align 41.47 +.global _interrupt_count1.48 +_interrupt_count:1.49 + .long 0x000000001.50 +.global _interrupt_pc1.51 +_interrupt_pc:1.52 + .long 0x000000001.53 +bl_mask:1.54 + .long 0x100000001.55 +1.56 +.global _install_interrupt_handler1.57 +_install_interrupt_handler:1.58 + stc vbr, r11.59 + mova old_vbr, r01.60 + mov.l r1, @r01.61 + mova __interrupt_handler, r01.62 + ldc r0, vbr1.63 + rts1.64 + nop1.65 +1.66 +.global _remove_interrupt_handler1.67 +_remove_interrupt_handler:1.68 + mov.l old_vbr, r11.69 + ldc r1, vbr1.70 + rts1.71 + nop1.72 +.align 41.73 +old_vbr:1.74 + .long 0x000000001.75 +expected_intevt:1.76 + .long 0x000000001.77 +expected_expevt:1.78 + .long 0x000000001.79 +1.80 +1.81 +__interrupt_handler:1.82 + .skip 0x1001.83 +general_exception:1.84 + mov.l handler_stack_ptr_k, r151.85 + mov.l @r15, r151.86 + mov.l r0, @-r151.87 + mov.l r1, @-r151.88 + mov.l r2, @-r151.89 +1.90 + mov.l expevt_k, r01.91 + mov.l @r0, r11.92 + mov.l expected_expevt_k, r21.93 + mov.l @r2, r21.94 + cmp/eq r1, r21.95 + bf general_not_expected1.96 + bra ex_expected1.97 + nop1.98 +general_not_expected:1.99 + bra ex_dontcare1.100 + nop1.101 + nop1.102 +expevt_k:1.103 + .long 0xFF0000241.104 +expected_expevt_k:1.105 + .long expected_expevt1.106 +handler_stack_ptr_k:1.107 + .long handler_stack_ptr1.108 + .skip 0x2D4 ! Pad up to 0x4001.109 +1.110 +tlb_exception:1.111 + mov.l handler_stack_ptr, r151.112 + mov.l r0, @-r151.113 + mov.l r1, @-r151.114 + mov.l r2, @-r151.115 +1.116 + mov.l expevt1_k, r01.117 + mov.l @r0, r11.118 + mov.l expected_expevt1_k, r21.119 + mov.l @r2, r21.120 + cmp/eq r1, r21.121 + bf tlb_not_expected1.122 + bra ex_expected1.123 + nop1.124 +tlb_not_expected:1.125 + bra ex_dontcare1.126 + nop1.127 +expevt1_k:1.128 + .long 0xFF0000241.129 +expected_expevt1_k:1.130 + .long expected_expevt1.131 +1.132 + .skip 0x1DC ! Pad up to 0x6001.133 +1.134 +irq_raised:1.135 + mov.l handler_stack_ptr, r151.136 + mov.l r0, @-r151.137 + mov.l r1, @-r151.138 + mov.l r2, @-r151.139 +1.140 + mov.l intevt_k, r01.141 + mov.l @r0, r11.142 + mov.l expected_intevt_k, r21.143 + mov.l @r2, r21.144 + cmp/eq r1, r21.145 + bf ex_dontcare1.146 +1.147 +ex_expected:1.148 + mov.l interrupt_count_k, r01.149 + mov.l @r0, r21.150 + add #1, r21.151 + mov.l r2, @r01.152 + stc spc, r21.153 + mov.l interrupt_pc_k, r01.154 + mov.l r2, @r01.155 +1.156 +! For most instructions, spc = raising instruction, so add 2 to get the next1.157 +! instruction. Exceptions are the slot illegals (need pc+4), and trapa/1.158 +! user-break-after-instruction where the pc is already correct1.159 + mov.l slot_illegal_k, r01.160 + cmp/eq r0, r11.161 + bt ex_slot_spc1.162 + mov.l slot_fpu_disable_k, r01.163 + cmp/eq r0, r11.164 + bt ex_slot_spc1.165 + mov.l trapa_exc_k, r01.166 + cmp/eq r0, r11.167 + bt ex_nochain1.168 + mov.l break_after_k, r01.169 + cmp/eq r0, r11.170 + bt ex_nochain1.171 +! For everything else, spc += 21.172 + add #2, r21.173 + ldc r2, spc1.174 + bra ex_nochain1.175 + nop1.176 +ex_slot_spc:1.177 + add #4, r21.178 + ldc r2, spc1.179 + bra ex_nochain1.180 + nop1.181 +1.182 +ex_dontcare: ! Not the event we were waiting for.1.183 + mov.l old_vbr_k, r21.184 + mov.l @r2, r21.185 + xor r0, r01.186 + cmp/eq r0, r21.187 + bt ex_nochain1.188 +1.189 + stc ssr, r01.190 + mov.l r0, @-r151.191 + stc spc, r01.192 + mov.l r0, @-r151.193 + stc sgr, r01.194 + mov.l r0, @-r151.195 + mov.l ex_chainreturn, r01.196 + ldc r0, spc1.197 + mova handler_stack_ptr, r01.198 + mov.l r15, @r01.199 + braf r2 ! Chain on1.200 + nop1.201 +1.202 +ex_chainreturn:1.203 + mov.l handler_stack_ptr, r151.204 + mov.l @r15+, r01.205 + ldc r0, sgr1.206 + mov.l @r15+, r01.207 + ldc r0, spc1.208 + mov.l @r15+, r01.209 + ldc r0, ssr1.210 +1.211 +ex_nochain: ! No previous vbr to chain to1.212 + mova handler_stack_ptr, r01.213 + mov r15, r11.214 + add #12, r11.215 + mov.l r1, @r01.216 + mov.l @r15+, r21.217 + mov.l @r15+, r11.218 + mov.l @r15+, r01.219 + rte1.220 + stc sgr, r151.221 +1.222 +.align 41.223 +expected_intevt_k:1.224 + .long expected_intevt1.225 +interrupt_count_k:1.226 + .long _interrupt_count1.227 +interrupt_pc_k:1.228 + .long _interrupt_pc1.229 +old_vbr_k:1.230 + .long old_vbr1.231 +trapa_k:1.232 + .long 0xFF0000201.233 +intevt_k:1.234 + .long 0xFF0000281.235 +1.236 +slot_illegal_k:1.237 + .long 0x000001A01.238 +slot_fpu_disable_k:1.239 + .long 0x000008201.240 +trapa_exc_k:1.241 + .long 0x000001601.242 +break_after_k:1.243 + .long 0x000001E01.244 +1.245 +handler_stack_ptr:1.246 + .long handler_stack_end1.247 +1.248 +handler_stack:1.249 + .skip 0x2001.250 +handler_stack_end:
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