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lxdream.org :: lxdream/src/asic.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 279:7bb759c23271
prev255:ade289880b8d
next302:96b5cc24309c
author nkeynes
date Sun Jan 14 02:54:40 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Initial SPU dma implementation
file annotate diff log raw
1.1 --- a/src/asic.c Thu Dec 21 11:12:19 2006 +0000
1.2 +++ b/src/asic.c Sun Jan 14 02:54:40 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: asic.c,v 1.22 2006-12-21 11:12:19 nkeynes Exp $
1.6 + * $Id: asic.c,v 1.23 2007-01-14 02:54:40 nkeynes Exp $
1.7 *
1.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
1.9 * and DMA).
1.10 @@ -179,6 +179,32 @@
1.11 intc_clear_interrupt( INT_IRQ9 );
1.12 }
1.13
1.14 +void g2_dma_transfer( int channel )
1.15 +{
1.16 + uint32_t offset = channel << 5;
1.17 +
1.18 + if( MMIO_READ( EXTDMA, SPUDMA0CTL1 + offset ) == 1 ) {
1.19 + if( MMIO_READ( EXTDMA, SPUDMA0CTL2 + offset ) == 1 ) {
1.20 + uint32_t extaddr = MMIO_READ( EXTDMA, SPUDMA0EXT + offset );
1.21 + uint32_t sh4addr = MMIO_READ( EXTDMA, SPUDMA0SH4 + offset );
1.22 + uint32_t length = MMIO_READ( EXTDMA, SPUDMA0SIZ + offset ) & 0x1FFFFFFF;
1.23 + uint32_t dir = MMIO_READ( EXTDMA, SPUDMA0DIR + offset );
1.24 + uint32_t mode = MMIO_READ( EXTDMA, SPUDMA0MOD + offset );
1.25 + char buf[length];
1.26 + if( dir == 0 ) { /* SH4 to device */
1.27 + mem_copy_from_sh4( buf, sh4addr, length );
1.28 + mem_copy_to_sh4( extaddr, buf, length );
1.29 + } else { /* Device to SH4 */
1.30 + mem_copy_from_sh4( buf, extaddr, length );
1.31 + mem_copy_to_sh4( sh4addr, buf, length );
1.32 + }
1.33 + MMIO_WRITE( EXTDMA, SPUDMA0CTL2 + offset, 0 );
1.34 + asic_event( EVENT_SPU_DMA0 + channel );
1.35 + } else {
1.36 + MMIO_WRITE( EXTDMA, SPUDMA0CTL2 + offset, 0 );
1.37 + }
1.38 + }
1.39 +}
1.40
1.41 void asic_ide_dma_transfer( )
1.42 {
1.43 @@ -328,7 +354,6 @@
1.44 }
1.45 break;
1.46 case IDEDMACTL1:
1.47 - MMIO_WRITE( EXTDMA, reg, val );
1.48 case IDEDMACTL2:
1.49 MMIO_WRITE( EXTDMA, reg, val );
1.50 asic_ide_dma_transfer( );
1.51 @@ -342,6 +367,44 @@
1.52 } else if( val == 0x000042FE ) {
1.53 idereg.interface_enabled = FALSE;
1.54 }
1.55 + break;
1.56 + case SPUDMA0CTL1:
1.57 + case SPUDMA0CTL2:
1.58 + MMIO_WRITE( EXTDMA, reg, val );
1.59 + g2_dma_transfer( 0 );
1.60 + break;
1.61 + case SPUDMA0UN1:
1.62 + break;
1.63 + case SPUDMA1CTL1:
1.64 + case SPUDMA1CTL2:
1.65 + MMIO_WRITE( EXTDMA, reg, val );
1.66 + g2_dma_transfer( 1 );
1.67 + break;
1.68 +
1.69 + case SPUDMA1UN1:
1.70 + break;
1.71 + case SPUDMA2CTL1:
1.72 + case SPUDMA2CTL2:
1.73 + MMIO_WRITE( EXTDMA, reg, val );
1.74 + g2_dma_transfer( 2 );
1.75 + break;
1.76 + case SPUDMA2UN1:
1.77 + break;
1.78 + case SPUDMA3CTL1:
1.79 + case SPUDMA3CTL2:
1.80 + MMIO_WRITE( EXTDMA, reg, val );
1.81 + g2_dma_transfer( 3 );
1.82 + break;
1.83 + case SPUDMA3UN1:
1.84 + break;
1.85 + case PVRDMA2CTL1:
1.86 + case PVRDMA2CTL2:
1.87 + if( val != 0 ) {
1.88 + ERROR( "Write to unimplemented DMA control register %08X", reg );
1.89 + //dreamcast_stop();
1.90 + //sh4_stop();
1.91 + }
1.92 + break;
1.93 default:
1.94 MMIO_WRITE( EXTDMA, reg, val );
1.95 }
.