1.1 --- a/src/asic.c Thu Dec 21 11:12:19 2006 +0000
1.2 +++ b/src/asic.c Sun Jan 14 02:54:40 2007 +0000
1.5 - * $Id: asic.c,v 1.22 2006-12-21 11:12:19 nkeynes Exp $
1.6 + * $Id: asic.c,v 1.23 2007-01-14 02:54:40 nkeynes Exp $
1.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
1.10 @@ -179,6 +179,32 @@
1.11 intc_clear_interrupt( INT_IRQ9 );
1.14 +void g2_dma_transfer( int channel )
1.16 + uint32_t offset = channel << 5;
1.18 + if( MMIO_READ( EXTDMA, SPUDMA0CTL1 + offset ) == 1 ) {
1.19 + if( MMIO_READ( EXTDMA, SPUDMA0CTL2 + offset ) == 1 ) {
1.20 + uint32_t extaddr = MMIO_READ( EXTDMA, SPUDMA0EXT + offset );
1.21 + uint32_t sh4addr = MMIO_READ( EXTDMA, SPUDMA0SH4 + offset );
1.22 + uint32_t length = MMIO_READ( EXTDMA, SPUDMA0SIZ + offset ) & 0x1FFFFFFF;
1.23 + uint32_t dir = MMIO_READ( EXTDMA, SPUDMA0DIR + offset );
1.24 + uint32_t mode = MMIO_READ( EXTDMA, SPUDMA0MOD + offset );
1.26 + if( dir == 0 ) { /* SH4 to device */
1.27 + mem_copy_from_sh4( buf, sh4addr, length );
1.28 + mem_copy_to_sh4( extaddr, buf, length );
1.29 + } else { /* Device to SH4 */
1.30 + mem_copy_from_sh4( buf, extaddr, length );
1.31 + mem_copy_to_sh4( sh4addr, buf, length );
1.33 + MMIO_WRITE( EXTDMA, SPUDMA0CTL2 + offset, 0 );
1.34 + asic_event( EVENT_SPU_DMA0 + channel );
1.36 + MMIO_WRITE( EXTDMA, SPUDMA0CTL2 + offset, 0 );
1.41 void asic_ide_dma_transfer( )
1.47 - MMIO_WRITE( EXTDMA, reg, val );
1.49 MMIO_WRITE( EXTDMA, reg, val );
1.50 asic_ide_dma_transfer( );
1.51 @@ -342,6 +367,44 @@
1.52 } else if( val == 0x000042FE ) {
1.53 idereg.interface_enabled = FALSE;
1.58 + MMIO_WRITE( EXTDMA, reg, val );
1.59 + g2_dma_transfer( 0 );
1.65 + MMIO_WRITE( EXTDMA, reg, val );
1.66 + g2_dma_transfer( 1 );
1.73 + MMIO_WRITE( EXTDMA, reg, val );
1.74 + g2_dma_transfer( 2 );
1.80 + MMIO_WRITE( EXTDMA, reg, val );
1.81 + g2_dma_transfer( 3 );
1.88 + ERROR( "Write to unimplemented DMA control register %08X", reg );
1.89 + //dreamcast_stop();
1.94 MMIO_WRITE( EXTDMA, reg, val );