1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/xlat/disasm/arm-dis.c Tue Mar 06 12:42:33 2012 +1000
1.4 +/* Instruction printing code for the ARM
1.5 + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
1.6 + 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
1.7 + Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
1.8 + Modification by James G. Smith (jsmith@cygnus.co.uk)
1.10 + This file is part of libopcodes.
1.12 + This library is free software; you can redistribute it and/or modify
1.13 + it under the terms of the GNU General Public License as published by
1.14 + the Free Software Foundation; either version 3 of the License, or
1.15 + (at your option) any later version.
1.17 + It is distributed in the hope that it will be useful, but WITHOUT
1.18 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
1.19 + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
1.20 + License for more details.
1.22 + You should have received a copy of the GNU General Public License
1.23 + along with this program; if not, write to the Free Software
1.24 + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
1.25 + MA 02110-1301, USA. */
1.27 +#include "sysdep.h"
1.29 +#include "dis-asm.h"
1.31 +#include "gettext.h"
1.32 +#include "safe-ctype.h"
1.33 +#include "floatformat.h"
1.35 +/* FIXME: Belongs in global header. */
1.37 +#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
1.40 +#define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
1.43 +#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
1.46 +/* Cached mapping symbol state. */
1.54 +struct arm_private_data
1.56 + /* The features to use when disassembling optional instructions. */
1.57 + arm_feature_set features;
1.59 + /* Whether any mapping symbols are present in the provided symbol
1.60 + table. -1 if we do not know yet, otherwise 0 or 1. */
1.61 + int has_mapping_symbols;
1.63 + /* Track the last type (although this doesn't seem to be useful) */
1.64 + enum map_type last_type;
1.66 + /* Tracking symbol table information */
1.67 + int last_mapping_sym;
1.68 + bfd_vma last_mapping_addr;
1.73 + unsigned long arch; /* Architecture defining this insn. */
1.74 + unsigned long value; /* If arch == 0 then value is a sentinel. */
1.75 + unsigned long mask; /* Recognise insn if (op & mask) == value. */
1.76 + const char * assembler; /* How to disassemble this insn. */
1.81 + unsigned long arch; /* Architecture defining this insn. */
1.82 + unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
1.83 + const char *assembler; /* How to disassemble this insn. */
1.86 +/* print_insn_coprocessor recognizes the following format control codes:
1.90 + %c print condition code (always bits 28-31 in ARM mode)
1.91 + %q print shifter argument
1.92 + %u print condition code (unconditional in ARM mode)
1.93 + %A print address for ldc/stc/ldf/stf instruction
1.94 + %B print vstm/vldm register list
1.95 + %I print cirrus signed shift immediate: bits 0..3|4..6
1.96 + %F print the COUNT field of a LFM/SFM instruction.
1.97 + %P print floating point precision in arithmetic insn
1.98 + %Q print floating point precision in ldf/stf insn
1.99 + %R print floating point rounding mode
1.101 + %<bitfield>r print as an ARM register
1.102 + %<bitfield>R as %<>r but r15 is UNPREDICTABLE
1.103 + %<bitfield>ru as %<>r but each u register must be unique.
1.104 + %<bitfield>d print the bitfield in decimal
1.105 + %<bitfield>k print immediate for VFPv3 conversion instruction
1.106 + %<bitfield>x print the bitfield in hex
1.107 + %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
1.108 + %<bitfield>f print a floating point constant if >7 else a
1.109 + floating point register
1.110 + %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
1.111 + %<bitfield>g print as an iWMMXt 64-bit register
1.112 + %<bitfield>G print as an iWMMXt general purpose or control register
1.113 + %<bitfield>D print as a NEON D register
1.114 + %<bitfield>Q print as a NEON Q register
1.116 + %y<code> print a single precision VFP reg.
1.117 + Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
1.118 + %z<code> print a double precision VFP reg
1.119 + Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
1.121 + %<bitfield>'c print specified char iff bitfield is all ones
1.122 + %<bitfield>`c print specified char iff bitfield is all zeroes
1.123 + %<bitfield>?ab... select from array of values in big endian order
1.125 + %L print as an iWMMXt N/M width field.
1.126 + %Z print the Immediate of a WSHUFH instruction.
1.127 + %l like 'A' except use byte offsets for 'B' & 'H'
1.129 + %i print 5-bit immediate in bits 8,3..0
1.130 + (print "32" when 0)
1.131 + %r print register offset address for wldt/wstr instruction. */
1.133 +enum opcode_sentinel_enum
1.135 + SENTINEL_IWMMXT_START = 1,
1.136 + SENTINEL_IWMMXT_END,
1.137 + SENTINEL_GENERIC_START
1.138 +} opcode_sentinels;
1.140 +#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
1.141 +#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
1.143 +/* Common coprocessor opcodes shared between Arm and Thumb-2. */
1.145 +static const struct opcode32 coprocessor_opcodes[] =
1.147 + /* XScale instructions. */
1.148 + {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
1.149 + {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
1.150 + {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
1.151 + {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
1.152 + {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
1.154 + /* Intel Wireless MMX technology instructions. */
1.155 + { 0, SENTINEL_IWMMXT_START, 0, "" },
1.156 + {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
1.157 + {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
1.158 + {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
1.159 + {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
1.160 + {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
1.161 + {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
1.162 + {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
1.163 + {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
1.164 + {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
1.165 + {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
1.166 + {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
1.167 + {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
1.168 + {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
1.169 + {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
1.170 + {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
1.171 + {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
1.172 + {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
1.173 + {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
1.174 + {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
1.175 + {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
1.176 + {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
1.177 + {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
1.178 + {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
1.179 + {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
1.180 + {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
1.181 + {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
1.182 + {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
1.183 + {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
1.184 + {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
1.185 + {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
1.186 + {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
1.187 + {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
1.188 + {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
1.189 + {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
1.190 + {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
1.191 + {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
1.192 + {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
1.193 + {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
1.194 + {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
1.195 + {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
1.196 + {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
1.197 + {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
1.198 + {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
1.199 + {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
1.200 + {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
1.201 + {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
1.202 + {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
1.203 + {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
1.204 + {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
1.205 + {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
1.206 + {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
1.207 + {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
1.208 + {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
1.209 + {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
1.210 + {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
1.211 + {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
1.212 + {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
1.213 + {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
1.214 + {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
1.215 + {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
1.216 + {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
1.217 + {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
1.218 + {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
1.219 + {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
1.220 + {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
1.221 + {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
1.222 + {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
1.223 + {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
1.224 + {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
1.225 + {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
1.226 + {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
1.227 + {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
1.228 + {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
1.229 + {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
1.230 + {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
1.231 + { 0, SENTINEL_IWMMXT_END, 0, "" },
1.233 + /* Floating point coprocessor (FPA) instructions. */
1.234 + {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.235 + {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.236 + {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.237 + {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.238 + {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.239 + {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.240 + {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.241 + {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.242 + {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.243 + {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.244 + {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.245 + {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.246 + {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
1.247 + {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
1.248 + {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
1.249 + {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
1.250 + {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
1.251 + {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
1.252 + {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
1.253 + {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
1.254 + {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
1.255 + {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
1.256 + {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
1.257 + {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
1.258 + {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
1.259 + {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
1.260 + {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
1.261 + {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
1.262 + {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
1.263 + {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
1.264 + {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
1.265 + {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
1.266 + {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
1.267 + {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
1.268 + {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
1.269 + {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
1.270 + {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
1.271 + {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
1.272 + {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
1.273 + {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
1.274 + {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
1.275 + {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
1.276 + {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
1.278 + /* Register load/store. */
1.279 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
1.280 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
1.281 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
1.282 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
1.283 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
1.284 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
1.285 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
1.286 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
1.287 + {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
1.288 + {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
1.289 + {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
1.290 + {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
1.291 + {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
1.292 + {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
1.293 + {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
1.294 + {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
1.296 + {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
1.297 + {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
1.298 + {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
1.299 + {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
1.301 + /* Data transfer between ARM and NEON registers. */
1.302 + {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1.303 + {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1.304 + {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1.305 + {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1.306 + {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1.307 + {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1.308 + {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
1.309 + {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
1.310 + {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
1.311 + {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
1.312 + {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
1.313 + {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
1.314 + {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
1.315 + {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
1.316 + /* Half-precision conversion instructions. */
1.317 + {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
1.318 + {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
1.320 + /* Floating point coprocessor (VFP) instructions. */
1.321 + {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
1.322 + {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
1.323 + {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
1.324 + {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
1.325 + {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
1.326 + {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
1.327 + {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
1.328 + {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
1.329 + {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
1.330 + {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
1.331 + {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
1.332 + {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
1.333 + {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
1.334 + {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
1.335 + {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
1.336 + {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
1.337 + {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
1.338 + {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
1.339 + {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
1.340 + {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
1.341 + {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
1.342 + {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
1.343 + {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
1.344 + {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
1.345 + {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
1.346 + {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
1.347 + {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
1.348 + {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
1.349 + {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
1.350 + {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
1.351 + {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
1.352 + {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
1.353 + {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
1.354 + {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
1.355 + {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
1.356 + {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
1.357 + {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
1.358 + {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1.359 + {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
1.360 + {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
1.361 + {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
1.362 + {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
1.363 + {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
1.364 + {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
1.365 + {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
1.366 + {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
1.367 + {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
1.368 + {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
1.369 + {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
1.370 + {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
1.371 + {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
1.372 + {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
1.373 + {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
1.374 + {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
1.375 + {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
1.376 + {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
1.377 + {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
1.378 + {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
1.379 + {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
1.380 + {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
1.381 + {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
1.382 + {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
1.383 + {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
1.384 + {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
1.385 + {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
1.386 + {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
1.387 + {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
1.389 + /* Cirrus coprocessor instructions. */
1.390 + {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1.391 + {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1.392 + {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1.393 + {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1.394 + {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1.395 + {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1.396 + {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1.397 + {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1.398 + {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1.399 + {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1.400 + {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1.401 + {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1.402 + {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1.403 + {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1.404 + {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1.405 + {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1.406 + {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
1.407 + {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
1.408 + {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
1.409 + {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
1.410 + {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
1.411 + {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
1.412 + {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
1.413 + {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
1.414 + {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1.415 + {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1.416 + {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1.417 + {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1.418 + {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1.419 + {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1.420 + {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1.421 + {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1.422 + {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1.423 + {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1.424 + {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1.425 + {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1.426 + {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1.427 + {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1.428 + {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1.429 + {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1.430 + {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1.431 + {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1.432 + {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1.433 + {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1.434 + {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1.435 + {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1.436 + {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1.437 + {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1.438 + {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1.439 + {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1.440 + {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1.441 + {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1.442 + {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1.443 + {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1.444 + {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1.445 + {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1.446 + {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1.447 + {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1.448 + {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1.449 + {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1.450 + {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1.451 + {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1.452 + {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1.453 + {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1.454 + {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1.455 + {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1.456 + {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1.457 + {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1.458 + {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1.459 + {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1.460 + {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1.461 + {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1.462 + {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1.463 + {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1.464 + {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1.465 + {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1.466 + {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1.467 + {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1.468 + {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1.469 + {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1.470 + {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1.471 + {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1.472 + {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1.473 + {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1.475 + /* VFP Fused multiply add instructions. */
1.476 + {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1.477 + {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1.478 + {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1.479 + {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1.480 + {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1.481 + {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1.482 + {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1.483 + {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1.485 + /* Generic coprocessor instructions. */
1.486 + { 0, SENTINEL_GENERIC_START, 0, "" },
1.487 + {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1.488 + {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1.489 + {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1.490 + {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1.491 + {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1.492 + {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1.493 + {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1.494 + {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1.496 + /* V6 coprocessor instructions. */
1.497 + {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1.498 + {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1.500 + /* V5 coprocessor instructions. */
1.501 + {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1.502 + {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1.503 + {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1.504 + {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1.505 + {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1.510 +/* Neon opcode table: This does not encode the top byte -- that is
1.511 + checked by the print_insn_neon routine, as it depends on whether we are
1.512 + doing thumb32 or arm32 disassembly. */
1.514 +/* print_insn_neon recognizes the following format control codes:
1.518 + %c print condition code
1.519 + %A print v{st,ld}[1234] operands
1.520 + %B print v{st,ld}[1234] any one operands
1.521 + %C print v{st,ld}[1234] single->all operands
1.523 + %E print vmov, vmvn, vorr, vbic encoded constant
1.524 + %F print vtbl,vtbx register list
1.526 + %<bitfield>r print as an ARM register
1.527 + %<bitfield>d print the bitfield in decimal
1.528 + %<bitfield>e print the 2^N - bitfield in decimal
1.529 + %<bitfield>D print as a NEON D register
1.530 + %<bitfield>Q print as a NEON Q register
1.531 + %<bitfield>R print as a NEON D or Q register
1.532 + %<bitfield>Sn print byte scaled width limited by n
1.533 + %<bitfield>Tn print short scaled width limited by n
1.534 + %<bitfield>Un print long scaled width limited by n
1.536 + %<bitfield>'c print specified char iff bitfield is all ones
1.537 + %<bitfield>`c print specified char iff bitfield is all zeroes
1.538 + %<bitfield>?ab... select from array of values in big endian order. */
1.540 +static const struct opcode32 neon_opcodes[] =
1.543 + {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1.544 + {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1.546 + /* Move data element to all lanes. */
1.547 + {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1.548 + {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1.549 + {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1.551 + /* Table lookup. */
1.552 + {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1.553 + {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1.555 + /* Half-precision conversions. */
1.556 + {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1.557 + {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1.559 + /* NEON fused multiply add instructions. */
1.560 + {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.561 + {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.563 + /* Two registers, miscellaneous. */
1.564 + {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1.565 + {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1.566 + {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1.567 + {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1.568 + {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1.569 + {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1.570 + {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1.571 + {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1.572 + {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1.573 + {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1.574 + {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1.575 + {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1.576 + {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1.577 + {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1.578 + {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1.579 + {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1.580 + {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1.581 + {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1.582 + {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1.583 + {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1.584 + {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1.585 + {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1.586 + {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1.587 + {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1.588 + {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1.589 + {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1.590 + {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1.591 + {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1.592 + {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1.593 + {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1.594 + {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1.595 + {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1.596 + {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1.598 + /* Three registers of the same length. */
1.599 + {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.600 + {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.601 + {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.602 + {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.603 + {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.604 + {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.605 + {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.606 + {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.607 + {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.608 + {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.609 + {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.610 + {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.611 + {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.612 + {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.613 + {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.614 + {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.615 + {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.616 + {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.617 + {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.618 + {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.619 + {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.620 + {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.621 + {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.622 + {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.623 + {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.624 + {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.625 + {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.626 + {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.627 + {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.628 + {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.629 + {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.630 + {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.631 + {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.632 + {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.633 + {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.634 + {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.635 + {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.636 + {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.637 + {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.638 + {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.639 + {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.640 + {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.641 + {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1.642 + {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1.643 + {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1.644 + {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1.645 + {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.646 + {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.647 + {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.648 + {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.649 + {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.650 + {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.651 + {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1.653 + /* One register and an immediate value. */
1.654 + {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1.655 + {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1.656 + {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1.657 + {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1.658 + {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1.659 + {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1.660 + {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1.661 + {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1.662 + {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1.663 + {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1.664 + {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1.665 + {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1.666 + {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1.668 + /* Two registers and a shift amount. */
1.669 + {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1.670 + {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1.671 + {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1.672 + {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1.673 + {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1.674 + {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1.675 + {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
1.676 + {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1.677 + {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1.678 + {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1.679 + {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1.680 + {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1.681 + {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1.682 + {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1.683 + {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1.684 + {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1.685 + {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1.686 + {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
1.687 + {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1.688 + {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1.689 + {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1.690 + {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1.691 + {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1.692 + {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1.693 + {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1.694 + {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1.695 + {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1.696 + {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1.697 + {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1.698 + {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
1.699 + {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1.700 + {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1.701 + {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1.702 + {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1.703 + {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1.704 + {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1.705 + {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1.706 + {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1.707 + {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1.708 + {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1.709 + {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1.710 + {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1.711 + {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1.712 + {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1.713 + {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1.714 + {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1.715 + {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1.716 + {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1.717 + {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1.718 + {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1.719 + {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1.720 + {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1.721 + {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1.722 + {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1.723 + {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1.724 + {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1.725 + {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1.726 + {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1.728 + /* Three registers of different lengths. */
1.729 + {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1.730 + {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1.731 + {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1.732 + {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1.733 + {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1.734 + {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1.735 + {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1.736 + {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1.737 + {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1.738 + {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1.739 + {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1.740 + {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1.741 + {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1.742 + {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1.743 + {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1.744 + {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1.745 + {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1.747 + /* Two registers and a scalar. */
1.748 + {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1.749 + {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1.750 + {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1.751 + {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1.752 + {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1.753 + {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1.754 + {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1.755 + {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1.756 + {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1.757 + {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1.758 + {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1.759 + {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1.760 + {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1.761 + {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1.762 + {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1.763 + {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1.764 + {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1.765 + {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1.766 + {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1.767 + {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1.768 + {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1.769 + {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1.771 + /* Element and structure load/store. */
1.772 + {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1.773 + {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1.774 + {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1.775 + {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1.776 + {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1.777 + {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1.778 + {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1.779 + {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1.780 + {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1.781 + {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1.782 + {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1.783 + {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1.784 + {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1.785 + {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1.786 + {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1.787 + {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1.788 + {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1.789 + {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1.790 + {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1.795 +/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1.796 + ordered: they must be searched linearly from the top to obtain a correct
1.799 +/* print_insn_arm recognizes the following format control codes:
1.803 + %a print address for ldr/str instruction
1.804 + %s print address for ldr/str halfword/signextend instruction
1.805 + %S like %s but allow UNPREDICTABLE addressing
1.806 + %b print branch destination
1.807 + %c print condition code (always bits 28-31)
1.808 + %m print register mask for ldm/stm instruction
1.809 + %o print operand2 (immediate or register + shift)
1.810 + %p print 'p' iff bits 12-15 are 15
1.811 + %t print 't' iff bit 21 set and bit 24 clear
1.812 + %B print arm BLX(1) destination
1.813 + %C print the PSR sub type.
1.814 + %U print barrier type.
1.815 + %P print address for pli instruction.
1.817 + %<bitfield>r print as an ARM register
1.818 + %<bitfield>R as %r but r15 is UNPREDICTABLE
1.819 + %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1.820 + %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1.821 + %<bitfield>d print the bitfield in decimal
1.822 + %<bitfield>W print the bitfield plus one in decimal
1.823 + %<bitfield>x print the bitfield in hex
1.824 + %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
1.826 + %<bitfield>'c print specified char iff bitfield is all ones
1.827 + %<bitfield>`c print specified char iff bitfield is all zeroes
1.828 + %<bitfield>?ab... select from array of values in big endian order
1.830 + %e print arm SMI operand (bits 0..7,8..19).
1.831 + %E print the LSB and WIDTH fields of a BFI or BFC instruction.
1.832 + %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1.833 + %R print the SPSR/CPSR or banked register of an MRS. */
1.835 +static const struct opcode32 arm_opcodes[] =
1.837 + /* ARM instructions. */
1.838 + {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1.839 + {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1.840 + {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1.841 + {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1.842 + {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1.843 + {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1.844 + {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1.846 + /* Virtualization Extension instructions. */
1.847 + {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
1.848 + {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1.850 + /* Integer Divide Extension instructions. */
1.851 + {ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1.852 + {ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1.854 + /* MP Extension instructions. */
1.855 + {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"},
1.857 + /* V7 instructions. */
1.858 + {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
1.859 + {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1.860 + {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1.861 + {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1.862 + {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
1.864 + /* ARM V6T2 instructions. */
1.865 + {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1.866 + {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1.867 + {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1.868 + {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15R, %S"},
1.870 + {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1.871 + {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1.873 + {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1.874 + {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1.875 + {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1.876 + {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1.878 + /* ARM Security extension instructions. */
1.879 + {ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
1.881 + /* ARM V6K instructions. */
1.882 + {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
1.883 + {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1.884 + {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1.885 + {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1.886 + {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1.887 + {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1.888 + {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1.890 + /* ARM V6K NOP hints. */
1.891 + {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
1.892 + {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
1.893 + {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
1.894 + {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
1.895 + {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1.897 + /* ARM V6 instructions. */
1.898 + {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1.899 + {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1.900 + {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1.901 + {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1.902 + {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1.903 + {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1.904 + {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1.905 + {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1.906 + {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1.907 + {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1.908 + {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1.909 + {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1.910 + {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1.911 + {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1.912 + {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1.913 + {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1.914 + {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1.915 + {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1.916 + {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1.917 + {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1.918 + {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1.919 + {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1.920 + {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1.921 + {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1.922 + {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1.923 + {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1.924 + {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1.925 + {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1.926 + {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1.927 + {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1.928 + {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1.929 + {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1.930 + {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1.931 + {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1.932 + {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1.933 + {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1.934 + {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1.935 + {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1.936 + {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1.937 + {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1.938 + {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1.939 + {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1.940 + {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1.941 + {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1.942 + {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1.943 + {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1.944 + {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1.945 + {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1.946 + {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1.947 + {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1.948 + {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1.949 + {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1.950 + {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1.951 + {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1.952 + {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1.953 + {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1.954 + {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1.955 + {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1.956 + {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1.957 + {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1.958 + {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1.959 + {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1.960 + {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1.961 + {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1.962 + {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1.963 + {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1.964 + {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1.965 + {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1.966 + {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1.967 + {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1.968 + {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1.969 + {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1.970 + {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1.971 + {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1.972 + {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1.973 + {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1.974 + {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1.975 + {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1.976 + {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1.977 + {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1.978 + {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1.979 + {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1.980 + {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1.981 + {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1.982 + {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1.983 + {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1.984 + {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1.985 + {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1.986 + {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1.987 + {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1.988 + {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1.989 + {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1.990 + {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1.991 + {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1.992 + {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1.993 + {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1.994 + {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1.995 + {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1.996 + {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1.997 + {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1.998 + {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1.999 + {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1.1000 + {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1.1001 + {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1.1002 + {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1.1003 + {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1.1004 + {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1.1005 + {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1.1006 + {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1.1007 + {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1.1008 + {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1.1009 + {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1.1010 + {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1.1011 + {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1.1012 + {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1.1013 + {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1.1014 + {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1.1015 + {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1.1016 + {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1.1017 + {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1.1018 + {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1.1019 + {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
1.1021 + /* V5J instruction. */
1.1022 + {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
1.1024 + /* V5 Instructions. */
1.1025 + {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1.1026 + {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
1.1027 + {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1.1028 + {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1.1030 + /* V5E "El Segundo" Instructions. */
1.1031 + {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1.1032 + {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1.1033 + {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
1.1034 + {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1.1035 + {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1.1036 + {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1.1037 + {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1.1039 + {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1.1040 + {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1.1042 + {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1.1043 + {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1.1044 + {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1.1045 + {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1.1047 + {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
1.1048 + {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
1.1049 + {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
1.1050 + {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
1.1052 + {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
1.1053 + {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
1.1055 + {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
1.1056 + {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
1.1057 + {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
1.1058 + {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
1.1060 + /* ARM Instructions. */
1.1061 + {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
1.1063 + {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
1.1064 + {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
1.1065 + {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
1.1066 + {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
1.1067 + {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
1.1068 + {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
1.1070 + {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
1.1071 + {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
1.1072 + {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
1.1073 + {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
1.1075 + {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
1.1076 + {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
1.1077 + {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
1.1078 + {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
1.1080 + {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
1.1081 + {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
1.1082 + {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
1.1084 + {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
1.1085 + {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
1.1086 + {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
1.1088 + {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
1.1089 + {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
1.1090 + {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
1.1092 + {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1.1093 + {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1.1094 + {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
1.1096 + {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
1.1097 + {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
1.1098 + {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
1.1100 + {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
1.1101 + {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
1.1102 + {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
1.1104 + {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1.1105 + {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1.1106 + {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
1.1108 + {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1.1109 + {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1.1110 + {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
1.1112 + {ARM_EXT_VIRT, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
1.1113 + {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
1.1114 + {ARM_EXT_V3, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
1.1116 + {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
1.1117 + {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
1.1118 + {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
1.1120 + {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
1.1121 + {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
1.1122 + {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
1.1124 + {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
1.1125 + {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
1.1126 + {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
1.1128 + {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
1.1129 + {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
1.1130 + {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
1.1132 + {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
1.1133 + {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
1.1134 + {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
1.1136 + {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
1.1137 + {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
1.1138 + {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
1.1139 + {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
1.1140 + {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
1.1141 + {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
1.1142 + {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
1.1144 + {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
1.1145 + {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
1.1146 + {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
1.1148 + {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
1.1149 + {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
1.1150 + {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
1.1152 + {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
1.1153 + {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
1.1155 + {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
1.1157 + {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
1.1158 + {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
1.1160 + {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
1.1161 + {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
1.1162 + {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1.1163 + {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
1.1164 + {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
1.1165 + {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1.1166 + {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
1.1167 + {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
1.1170 + {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
1.1171 + {0, 0x00000000, 0x00000000, 0}
1.1174 +/* print_insn_thumb16 recognizes the following format control codes:
1.1176 + %S print Thumb register (bits 3..5 as high number if bit 6 set)
1.1177 + %D print Thumb register (bits 0..2 as high number if bit 7 set)
1.1178 + %<bitfield>I print bitfield as a signed decimal
1.1179 + (top bit of range being the sign bit)
1.1180 + %N print Thumb register mask (with LR)
1.1181 + %O print Thumb register mask (with PC)
1.1182 + %M print Thumb register mask
1.1183 + %b print CZB's 6-bit unsigned branch destination
1.1184 + %s print Thumb right-shift immediate (6..10; 0 == 32).
1.1185 + %c print the condition code
1.1186 + %C print the condition code, or "s" if not conditional
1.1187 + %x print warning if conditional an not at end of IT block"
1.1188 + %X print "\t; unpredictable <IT:code>" if conditional
1.1189 + %I print IT instruction suffix and operands
1.1190 + %W print Thumb Writeback indicator for LDMIA
1.1191 + %<bitfield>r print bitfield as an ARM register
1.1192 + %<bitfield>d print bitfield as a decimal
1.1193 + %<bitfield>H print (bitfield * 2) as a decimal
1.1194 + %<bitfield>W print (bitfield * 4) as a decimal
1.1195 + %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
1.1196 + %<bitfield>B print Thumb branch destination (signed displacement)
1.1197 + %<bitfield>c print bitfield as a condition code
1.1198 + %<bitnum>'c print specified char iff bit is one
1.1199 + %<bitnum>?ab print a if bit is one else print b. */
1.1201 +static const struct opcode16 thumb_opcodes[] =
1.1203 + /* Thumb instructions. */
1.1205 + /* ARM V6K no-argument instructions. */
1.1206 + {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
1.1207 + {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
1.1208 + {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
1.1209 + {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
1.1210 + {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
1.1211 + {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
1.1213 + /* ARM V6T2 instructions. */
1.1214 + {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
1.1215 + {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
1.1216 + {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
1.1219 + {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
1.1220 + {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
1.1221 + {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
1.1222 + {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
1.1223 + {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
1.1224 + {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
1.1225 + {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
1.1226 + {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
1.1227 + {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
1.1228 + {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
1.1229 + {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
1.1231 + /* ARM V5 ISA extends Thumb. */
1.1232 + {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
1.1233 + /* This is BLX(2). BLX(1) is a 32-bit instruction. */
1.1234 + {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
1.1235 + /* ARM V4T ISA (Thumb v1). */
1.1236 + {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
1.1238 + {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
1.1239 + {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
1.1240 + {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
1.1241 + {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
1.1242 + {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
1.1243 + {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
1.1244 + {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
1.1245 + {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
1.1246 + {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
1.1247 + {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
1.1248 + {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
1.1249 + {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
1.1250 + {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
1.1251 + {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
1.1252 + {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
1.1253 + {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
1.1255 + {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
1.1256 + {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
1.1258 + {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
1.1259 + {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
1.1260 + {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
1.1261 + {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
1.1263 + {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
1.1264 + {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
1.1266 + {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
1.1267 + {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
1.1268 + {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
1.1269 + {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
1.1271 + {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
1.1272 + {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
1.1273 + {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
1.1275 + {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1.1276 + {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1.1278 + {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
1.1279 + {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
1.1280 + {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
1.1281 + {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
1.1283 + {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
1.1284 + {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
1.1285 + {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
1.1286 + {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
1.1288 + {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
1.1290 + {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
1.1291 + {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
1.1292 + {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
1.1293 + {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
1.1295 + {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
1.1296 + {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
1.1298 + {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
1.1299 + {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
1.1301 + {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
1.1302 + {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
1.1304 + {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
1.1305 + {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
1.1307 + {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
1.1309 + {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
1.1310 + {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
1.1312 + {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
1.1314 + /* The E800 .. FFFF range is unconditionally redirected to the
1.1315 + 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
1.1316 + are processed via that table. Thus, we can never encounter a
1.1317 + bare "second half of BL/BLX(1)" instruction here. */
1.1318 + {ARM_EXT_V1, 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
1.1322 +/* Thumb32 opcodes use the same table structure as the ARM opcodes.
1.1323 + We adopt the convention that hw1 is the high 16 bits of .value and
1.1324 + .mask, hw2 the low 16 bits.
1.1326 + print_insn_thumb32 recognizes the following format control codes:
1.1330 + %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
1.1331 + %M print a modified 12-bit immediate (same location)
1.1332 + %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
1.1333 + %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
1.1334 + %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
1.1335 + %S print a possibly-shifted Rm
1.1337 + %L print address for a ldrd/strd instruction
1.1338 + %a print the address of a plain load/store
1.1339 + %w print the width and signedness of a core load/store
1.1340 + %m print register mask for ldm/stm
1.1342 + %E print the lsb and width fields of a bfc/bfi instruction
1.1343 + %F print the lsb and width fields of a sbfx/ubfx instruction
1.1344 + %b print a conditional branch offset
1.1345 + %B print an unconditional branch offset
1.1346 + %s print the shift field of an SSAT instruction
1.1347 + %R print the rotation field of an SXT instruction
1.1348 + %U print barrier type.
1.1349 + %P print address for pli instruction.
1.1350 + %c print the condition code
1.1351 + %x print warning if conditional an not at end of IT block"
1.1352 + %X print "\t; unpredictable <IT:code>" if conditional
1.1354 + %<bitfield>d print bitfield in decimal
1.1355 + %<bitfield>W print bitfield*4 in decimal
1.1356 + %<bitfield>r print bitfield as an ARM register
1.1357 + %<bitfield>R as %<>r bit r15 is UNPREDICTABLE
1.1358 + %<bitfield>c print bitfield as a condition code
1.1360 + %<bitfield>'c print specified char iff bitfield is all ones
1.1361 + %<bitfield>`c print specified char iff bitfield is all zeroes
1.1362 + %<bitfield>?ab... select from array of values in big endian order
1.1364 + With one exception at the bottom (done because BL and BLX(1) need
1.1365 + to come dead last), this table was machine-sorted first in
1.1366 + decreasing order of number of bits set in the mask, then in
1.1367 + increasing numeric order of mask, then in increasing numeric order
1.1368 + of opcode. This order is not the clearest for a human reader, but
1.1369 + is guaranteed never to catch a special-case bit pattern with a more
1.1370 + general mask, which is important, because this instruction encoding
1.1371 + makes heavy use of special-case bit patterns. */
1.1372 +static const struct opcode32 thumb32_opcodes[] =
1.1374 + /* V7 instructions. */
1.1375 + {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
1.1376 + {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
1.1377 + {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
1.1378 + {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
1.1379 + {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
1.1380 + {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
1.1381 + {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
1.1383 + /* Virtualization Extension instructions. */
1.1384 + {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
1.1385 + /* We skip ERET as that is SUBS pc, lr, #0. */
1.1387 + /* MP Extension instructions. */
1.1388 + {ARM_EXT_MP, 0xf830f000, 0xff70f000, "pldw%c\t%a"},
1.1390 + /* Security extension instructions. */
1.1391 + {ARM_EXT_SEC, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
1.1393 + /* Instructions defined in the basic V6T2 set. */
1.1394 + {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
1.1395 + {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
1.1396 + {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
1.1397 + {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
1.1398 + {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"},
1.1399 + {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
1.1401 + {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
1.1402 + {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
1.1403 + {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
1.1404 + {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
1.1405 + {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
1.1406 + {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
1.1407 + {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
1.1408 + {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
1.1409 + {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
1.1410 + {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
1.1411 + {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
1.1412 + {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
1.1413 + {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
1.1414 + {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
1.1415 + {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
1.1416 + {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
1.1417 + {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
1.1418 + {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
1.1419 + {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
1.1420 + {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
1.1421 + {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
1.1422 + {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
1.1423 + {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
1.1424 + {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
1.1425 + {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
1.1426 + {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
1.1427 + {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
1.1428 + {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
1.1429 + {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
1.1430 + {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
1.1431 + {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
1.1432 + {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
1.1433 + {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
1.1434 + {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
1.1435 + {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
1.1436 + {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
1.1437 + {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
1.1438 + {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
1.1439 + {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
1.1440 + {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
1.1441 + {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
1.1442 + {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
1.1443 + {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
1.1444 + {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
1.1445 + {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
1.1446 + {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
1.1447 + {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
1.1448 + {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
1.1449 + {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
1.1450 + {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
1.1451 + {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
1.1452 + {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
1.1453 + {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
1.1454 + {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
1.1455 + {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
1.1456 + {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
1.1457 + {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
1.1458 + {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
1.1459 + {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
1.1460 + {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
1.1461 + {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
1.1462 + {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
1.1463 + {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
1.1464 + {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
1.1465 + {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
1.1466 + {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
1.1467 + {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
1.1468 + {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
1.1469 + {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
1.1470 + {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
1.1471 + {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
1.1472 + {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
1.1473 + {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
1.1474 + {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
1.1475 + {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1.1476 + {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1.1477 + {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1.1478 + {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1.1479 + {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
1.1480 + {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
1.1481 + {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
1.1482 + {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
1.1483 + {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1.1484 + {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
1.1485 + {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
1.1486 + {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1.1487 + {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1.1488 + {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1.1489 + {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1.1490 + {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1.1491 + {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1.1492 + {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1.1493 + {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
1.1494 + {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
1.1495 + {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
1.1496 + {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
1.1497 + {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
1.1498 + {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
1.1499 + {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
1.1500 + {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
1.1501 + {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
1.1502 + {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
1.1503 + {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
1.1504 + {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
1.1505 + {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1.1506 + {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1.1507 + {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1.1508 + {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1.1509 + {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1.1510 + {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1.1511 + {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1.1512 + {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1.1513 + {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
1.1514 + {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
1.1515 + {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
1.1516 + {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
1.1517 + {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1.1518 + {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1.1519 + {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1.1520 + {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1.1521 + {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1.1522 + {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1.1523 + {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1.1524 + {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
1.1525 + {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
1.1526 + {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
1.1527 + {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
1.1528 + {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
1.1529 + {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1.1530 + {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1.1531 + {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
1.1532 + {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
1.1533 + {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
1.1534 + {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
1.1535 + {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
1.1536 + {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
1.1537 + {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
1.1538 + {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
1.1539 + {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
1.1540 + {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
1.1541 + {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
1.1542 + {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
1.1543 + {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
1.1544 + {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
1.1545 + {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
1.1546 + {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
1.1547 + {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
1.1548 + {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
1.1549 + {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
1.1550 + {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
1.1551 + {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
1.1552 + {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
1.1553 + {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
1.1554 + {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
1.1555 + {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
1.1556 + {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
1.1557 + {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
1.1558 + {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
1.1559 + {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
1.1560 + {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
1.1561 + {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
1.1562 + {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
1.1563 + {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
1.1564 + {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
1.1565 + {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
1.1566 + {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1.1567 + {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1.1568 + {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1.1569 + {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1.1570 + {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
1.1571 + {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
1.1573 + /* Filter out Bcc with cond=E or F, which are used for other instructions. */
1.1574 + {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
1.1575 + {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
1.1576 + {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
1.1577 + {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
1.1579 + /* These have been 32-bit since the invention of Thumb. */
1.1580 + {ARM_EXT_V4T, 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
1.1581 + {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
1.1584 + {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
1.1588 +static const char *const arm_conditional[] =
1.1589 +{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
1.1590 + "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
1.1592 +static const char *const arm_fp_const[] =
1.1593 +{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
1.1595 +static const char *const arm_shift[] =
1.1596 +{"lsl", "lsr", "asr", "ror"};
1.1601 + const char *description;
1.1602 + const char *reg_names[16];
1.1606 +static const arm_regname regnames[] =
1.1608 + { "raw" , "Select raw register names",
1.1609 + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
1.1610 + { "gcc", "Select register names used by GCC",
1.1611 + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
1.1612 + { "std", "Select register names used in ARM's ISA documentation",
1.1613 + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
1.1614 + { "apcs", "Select register names used in the APCS",
1.1615 + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
1.1616 + { "atpcs", "Select register names used in the ATPCS",
1.1617 + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
1.1618 + { "special-atpcs", "Select special register names used in the ATPCS",
1.1619 + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
1.1622 +static const char *const iwmmxt_wwnames[] =
1.1625 +static const char *const iwmmxt_wwssnames[] =
1.1626 +{"b", "bus", "bc", "bss",
1.1627 + "h", "hus", "hc", "hss",
1.1628 + "w", "wus", "wc", "wss",
1.1629 + "d", "dus", "dc", "dss"
1.1632 +static const char *const iwmmxt_regnames[] =
1.1633 +{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
1.1634 + "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
1.1637 +static const char *const iwmmxt_cregnames[] =
1.1638 +{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
1.1639 + "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
1.1642 +/* Default to GCC register name set. */
1.1643 +static unsigned int regname_selected = 1;
1.1645 +#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
1.1646 +#define arm_regnames regnames[regname_selected].reg_names
1.1648 +static bfd_boolean force_thumb = FALSE;
1.1650 +/* Current IT instruction state. This contains the same state as the IT
1.1652 +static unsigned int ifthen_state;
1.1653 +/* IT state for the next instruction. */
1.1654 +static unsigned int ifthen_next_state;
1.1655 +/* The address of the insn for which the IT state is valid. */
1.1656 +static bfd_vma ifthen_address;
1.1657 +#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
1.1662 +get_arm_regname_num_options (void)
1.1664 + return NUM_ARM_REGNAMES;
1.1668 +set_arm_regname_option (int option)
1.1670 + int old = regname_selected;
1.1671 + regname_selected = option;
1.1676 +get_arm_regnames (int option,
1.1677 + const char **setname,
1.1678 + const char **setdescription,
1.1679 + const char *const **register_names)
1.1681 + *setname = regnames[option].name;
1.1682 + *setdescription = regnames[option].description;
1.1683 + *register_names = regnames[option].reg_names;
1.1687 +/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
1.1688 + Returns pointer to following character of the format string and
1.1689 + fills in *VALUEP and *WIDTHP with the extracted value and number of
1.1690 + bits extracted. WIDTHP can be NULL. */
1.1693 +arm_decode_bitfield (const char *ptr,
1.1695 + unsigned long *valuep,
1.1698 + unsigned long value = 0;
1.1706 + for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
1.1707 + start = start * 10 + *ptr - '0';
1.1709 + for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
1.1710 + end = end * 10 + *ptr - '0';
1.1716 + value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
1.1719 + while (*ptr++ == ',');
1.1727 +arm_decode_shift (long given, fprintf_ftype func, void *stream,
1.1728 + bfd_boolean print_shift)
1.1730 + func (stream, "%s", arm_regnames[given & 0xf]);
1.1732 + if ((given & 0xff0) != 0)
1.1734 + if ((given & 0x10) == 0)
1.1736 + int amount = (given & 0xf80) >> 7;
1.1737 + int shift = (given & 0x60) >> 5;
1.1743 + func (stream, ", rrx");
1.1751 + func (stream, ", %s #%d", arm_shift[shift], amount);
1.1753 + func (stream, ", #%d", amount);
1.1755 + else if ((given & 0x80) == 0x80)
1.1756 + func (stream, "\t; <illegal shifter operand>");
1.1757 + else if (print_shift)
1.1758 + func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
1.1759 + arm_regnames[(given & 0xf00) >> 8]);
1.1761 + func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
1.1770 +#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
1.1771 +#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
1.1772 +#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
1.1773 +#define PRE_BIT_SET (given & (1 << P_BIT))
1.1775 +/* Print one coprocessor instruction on INFO->STREAM.
1.1776 + Return TRUE if the instuction matched, FALSE if this is not a
1.1777 + recognised coprocessor instruction. */
1.1780 +print_insn_coprocessor (bfd_vma pc,
1.1781 + struct disassemble_info *info,
1.1785 + const struct opcode32 *insn;
1.1786 + void *stream = info->stream;
1.1787 + fprintf_ftype func = info->fprintf_func;
1.1789 + unsigned long value = 0;
1.1790 + struct arm_private_data *private_data = info->private_data;
1.1791 + unsigned long allowed_arches = private_data->features.coproc;
1.1794 + for (insn = coprocessor_opcodes; insn->assembler; insn++)
1.1796 + unsigned long u_reg = 16;
1.1797 + bfd_boolean is_unpredictable = FALSE;
1.1798 + signed long value_in_comment = 0;
1.1804 + case SENTINEL_IWMMXT_START:
1.1805 + if (info->mach != bfd_mach_arm_XScale
1.1806 + && info->mach != bfd_mach_arm_iWMMXt
1.1807 + && info->mach != bfd_mach_arm_iWMMXt2)
1.1810 + while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END);
1.1813 + case SENTINEL_IWMMXT_END:
1.1816 + case SENTINEL_GENERIC_START:
1.1817 + allowed_arches = private_data->features.core;
1.1828 + /* The high 4 bits are 0xe for Arm conditional instructions, and
1.1829 + 0xe for arm unconditional instructions. The rest of the
1.1830 + encoding is the same. */
1.1840 + /* Only match unconditional instuctions against unconditional
1.1842 + if ((given & 0xf0000000) == 0xf0000000)
1.1849 + cond = (given >> 28) & 0xf;
1.1855 + if ((given & mask) != value)
1.1858 + if ((insn->arch & allowed_arches) == 0)
1.1861 + for (c = insn->assembler; *c; c++)
1.1873 + int rn = (given >> 16) & 0xf;
1.1874 + bfd_vma offset = given & 0xff;
1.1876 + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
1.1878 + if (PRE_BIT_SET || WRITEBACK_BIT_SET)
1.1880 + /* Not unindexed. The offset is scaled. */
1.1882 + if (NEGATIVE_BIT_SET)
1.1885 + value_in_comment = offset;
1.1891 + func (stream, ", #%d]%s",
1.1893 + WRITEBACK_BIT_SET ? "!" : "");
1.1894 + else if (NEGATIVE_BIT_SET)
1.1895 + func (stream, ", #-0]");
1.1903 + if (WRITEBACK_BIT_SET)
1.1906 + func (stream, ", #%d", offset);
1.1907 + else if (NEGATIVE_BIT_SET)
1.1908 + func (stream, ", #-0");
1.1912 + func (stream, ", {%s%d}",
1.1913 + (NEGATIVE_BIT_SET && !offset) ? "-" : "",
1.1915 + value_in_comment = offset;
1.1918 + if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
1.1920 + func (stream, "\t; ");
1.1921 + /* For unaligned PCs, apply off-by-alignment
1.1923 + info->print_address_func (offset + pc
1.1924 + + info->bytes_per_chunk * 2
1.1933 + int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
1.1934 + int offset = (given >> 1) & 0x3f;
1.1937 + func (stream, "{d%d}", regno);
1.1938 + else if (regno + offset > 32)
1.1939 + func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
1.1941 + func (stream, "{d%d-d%d}", regno, regno + offset - 1);
1.1946 + func (stream, "%s", arm_conditional[cond]);
1.1950 + /* Print a Cirrus/DSP shift immediate. */
1.1951 + /* Immediates are 7bit signed ints with bits 0..3 in
1.1952 + bits 0..3 of opcode and bits 4..6 in bits 5..7
1.1957 + imm = (given & 0xf) | ((given & 0xe0) >> 1);
1.1959 + /* Is ``imm'' a negative number? */
1.1963 + func (stream, "%d", imm);
1.1969 + switch (given & 0x00408000)
1.1986 + switch (given & 0x00080080)
1.1998 + func (stream, _("<illegal precision>"));
1.2004 + switch (given & 0x00408000)
1.2022 + switch (given & 0x60)
1.2038 + case '0': case '1': case '2': case '3': case '4':
1.2039 + case '5': case '6': case '7': case '8': case '9':
1.2043 + c = arm_decode_bitfield (c, given, &value, &width);
1.2049 + is_unpredictable = TRUE;
1.2054 + /* Eat the 'u' character. */
1.2058 + is_unpredictable = TRUE;
1.2061 + func (stream, "%s", arm_regnames[value]);
1.2064 + func (stream, "d%ld", value);
1.2068 + func (stream, "<illegal reg q%ld.5>", value >> 1);
1.2070 + func (stream, "q%ld", value >> 1);
1.2073 + func (stream, "%ld", value);
1.2074 + value_in_comment = value;
1.2078 + int from = (given & (1 << 7)) ? 32 : 16;
1.2079 + func (stream, "%ld", from - value);
1.2085 + func (stream, "#%s", arm_fp_const[value & 7]);
1.2087 + func (stream, "f%ld", value);
1.2092 + func (stream, "%s", iwmmxt_wwnames[value]);
1.2094 + func (stream, "%s", iwmmxt_wwssnames[value]);
1.2098 + func (stream, "%s", iwmmxt_regnames[value]);
1.2101 + func (stream, "%s", iwmmxt_cregnames[value]);
1.2105 + func (stream, "0x%lx", (value & 0xffffffffUL));
1.2111 + func (stream, "%c", *c);
1.2115 + if (value == ((1ul << width) - 1))
1.2116 + func (stream, "%c", *c);
1.2119 + func (stream, "%c", c[(1 << width) - (int) value]);
1.2130 + int single = *c++ == 'y';
1.2135 + case '4': /* Sm pair */
1.2136 + case '0': /* Sm, Dm */
1.2137 + regno = given & 0x0000000f;
1.2141 + regno += (given >> 5) & 1;
1.2144 + regno += ((given >> 5) & 1) << 4;
1.2147 + case '1': /* Sd, Dd */
1.2148 + regno = (given >> 12) & 0x0000000f;
1.2152 + regno += (given >> 22) & 1;
1.2155 + regno += ((given >> 22) & 1) << 4;
1.2158 + case '2': /* Sn, Dn */
1.2159 + regno = (given >> 16) & 0x0000000f;
1.2163 + regno += (given >> 7) & 1;
1.2166 + regno += ((given >> 7) & 1) << 4;
1.2171 + regno = (given >> 12) & 0x0000000f;
1.2175 + regno += (given >> 22) & 1;
1.2178 + regno += ((given >> 22) & 1) << 4;
1.2185 + func (stream, "%c%d", single ? 's' : 'd', regno);
1.2189 + int count = given & 0xff;
1.2196 + func (stream, "-%c%d",
1.2204 + func (stream, ", %c%d", single ? 's' : 'd',
1.2210 + switch (given & 0x00400100)
1.2212 + case 0x00000000: func (stream, "b"); break;
1.2213 + case 0x00400000: func (stream, "h"); break;
1.2214 + case 0x00000100: func (stream, "w"); break;
1.2215 + case 0x00400100: func (stream, "d"); break;
1.2223 + /* given (20, 23) | given (0, 3) */
1.2224 + value = ((given >> 16) & 0xf0) | (given & 0xf);
1.2225 + func (stream, "%d", value);
1.2230 + /* This is like the 'A' operator, except that if
1.2231 + the width field "M" is zero, then the offset is
1.2232 + *not* multiplied by four. */
1.2234 + int offset = given & 0xff;
1.2235 + int multiplier = (given & 0x00000100) ? 4 : 1;
1.2237 + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
1.2241 + value_in_comment = offset * multiplier;
1.2242 + if (NEGATIVE_BIT_SET)
1.2243 + value_in_comment = - value_in_comment;
1.2249 + func (stream, ", #%s%d]%s",
1.2250 + NEGATIVE_BIT_SET ? "-" : "",
1.2252 + WRITEBACK_BIT_SET ? "!" : "");
1.2254 + func (stream, "], #%s%d",
1.2255 + NEGATIVE_BIT_SET ? "-" : "",
1.2256 + offset * multiplier);
1.2265 + int imm4 = (given >> 4) & 0xf;
1.2266 + int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
1.2267 + int ubit = ! NEGATIVE_BIT_SET;
1.2268 + const char *rm = arm_regnames [given & 0xf];
1.2269 + const char *rn = arm_regnames [(given >> 16) & 0xf];
1.2275 + func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
1.2277 + func (stream, ", lsl #%d", imm4);
1.2284 + func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
1.2286 + func (stream, ", lsl #%d", imm4);
1.2288 + if (puw_bits == 5 || puw_bits == 7)
1.2293 + func (stream, "INVALID");
1.2301 + imm5 = ((given & 0x100) >> 4) | (given & 0xf);
1.2302 + func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
1.2312 + func (stream, "%c", *c);
1.2315 + if (value_in_comment > 32 || value_in_comment < -16)
1.2316 + func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
1.2318 + if (is_unpredictable)
1.2319 + func (stream, UNPREDICTABLE_INSTRUCTION);
1.2326 +/* Decodes and prints ARM addressing modes. Returns the offset
1.2327 + used in the address, if any, if it is worthwhile printing the
1.2328 + offset as a hexadecimal value in a comment at the end of the
1.2329 + line of disassembly. */
1.2332 +print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
1.2334 + void *stream = info->stream;
1.2335 + fprintf_ftype func = info->fprintf_func;
1.2338 + if (((given & 0x000f0000) == 0x000f0000)
1.2339 + && ((given & 0x02000000) == 0))
1.2341 + offset = given & 0xfff;
1.2343 + func (stream, "[pc");
1.2347 + /* Pre-indexed. Elide offset of positive zero when
1.2349 + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
1.2350 + func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", offset);
1.2352 + if (NEGATIVE_BIT_SET)
1.2357 + /* Cope with the possibility of write-back
1.2358 + being used. Probably a very dangerous thing
1.2359 + for the programmer to do, but who are we to
1.2361 + func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
1.2363 + else /* Post indexed. */
1.2365 + func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", offset);
1.2367 + /* Ie ignore the offset. */
1.2371 + func (stream, "\t; ");
1.2372 + info->print_address_func (offset, info);
1.2378 + arm_regnames[(given >> 16) & 0xf]);
1.2382 + if ((given & 0x02000000) == 0)
1.2384 + /* Elide offset of positive zero when non-writeback. */
1.2385 + offset = given & 0xfff;
1.2386 + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
1.2387 + func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", offset);
1.2391 + func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
1.2392 + arm_decode_shift (given, func, stream, TRUE);
1.2396 + WRITEBACK_BIT_SET ? "!" : "");
1.2400 + if ((given & 0x02000000) == 0)
1.2402 + /* Always show offset. */
1.2403 + offset = given & 0xfff;
1.2404 + func (stream, "], #%s%d",
1.2405 + NEGATIVE_BIT_SET ? "-" : "", offset);
1.2409 + func (stream, "], %s",
1.2410 + NEGATIVE_BIT_SET ? "-" : "");
1.2411 + arm_decode_shift (given, func, stream, TRUE);
1.2416 + return (signed long) offset;
1.2419 +/* Print one neon instruction on INFO->STREAM.
1.2420 + Return TRUE if the instuction matched, FALSE if this is not a
1.2421 + recognised neon instruction. */
1.2424 +print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
1.2426 + const struct opcode32 *insn;
1.2427 + void *stream = info->stream;
1.2428 + fprintf_ftype func = info->fprintf_func;
1.2432 + if ((given & 0xef000000) == 0xef000000)
1.2434 + /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
1.2435 + unsigned long bit28 = given & (1 << 28);
1.2443 + else if ((given & 0xff000000) == 0xf9000000)
1.2444 + given ^= 0xf9000000 ^ 0xf4000000;
1.2449 + for (insn = neon_opcodes; insn->assembler; insn++)
1.2451 + if ((given & insn->mask) == insn->value)
1.2453 + signed long value_in_comment = 0;
1.2456 + for (c = insn->assembler; *c; c++)
1.2467 + if (thumb && ifthen_state)
1.2468 + func (stream, "%s", arm_conditional[IFTHEN_COND]);
1.2473 + static const unsigned char enc[16] =
1.2475 + 0x4, 0x14, /* st4 0,1 */
1.2487 + int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
1.2488 + int rn = ((given >> 16) & 0xf);
1.2489 + int rm = ((given >> 0) & 0xf);
1.2490 + int align = ((given >> 4) & 0x3);
1.2491 + int type = ((given >> 8) & 0xf);
1.2492 + int n = enc[type] & 0xf;
1.2493 + int stride = (enc[type] >> 4) + 1;
1.2498 + for (ix = 0; ix != n; ix++)
1.2499 + func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
1.2501 + func (stream, "d%d", rd);
1.2503 + func (stream, "d%d-d%d", rd, rd + n - 1);
1.2504 + func (stream, "}, [%s", arm_regnames[rn]);
1.2506 + func (stream, " :%d", 32 << align);
1.2511 + func (stream, ", %s", arm_regnames[rm]);
1.2517 + int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
1.2518 + int rn = ((given >> 16) & 0xf);
1.2519 + int rm = ((given >> 0) & 0xf);
1.2520 + int idx_align = ((given >> 4) & 0xf);
1.2522 + int size = ((given >> 10) & 0x3);
1.2523 + int idx = idx_align >> (size + 1);
1.2524 + int length = ((given >> 8) & 3) + 1;
1.2528 + if (length > 1 && size > 0)
1.2529 + stride = (idx_align & (1 << size)) ? 2 : 1;
1.2535 + int amask = (1 << size) - 1;
1.2536 + if ((idx_align & (1 << size)) != 0)
1.2540 + if ((idx_align & amask) == amask)
1.2542 + else if ((idx_align & amask) != 0)
1.2549 + if (size == 2 && (idx_align & 2) != 0)
1.2551 + align = (idx_align & 1) ? 16 << size : 0;
1.2555 + if ((size == 2 && (idx_align & 3) != 0)
1.2556 + || (idx_align & 1) != 0)
1.2563 + if ((idx_align & 3) == 3)
1.2565 + align = (idx_align & 3) * 64;
1.2568 + align = (idx_align & 1) ? 32 << size : 0;
1.2576 + for (i = 0; i < length; i++)
1.2577 + func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
1.2578 + rd + i * stride, idx);
1.2579 + func (stream, "}, [%s", arm_regnames[rn]);
1.2581 + func (stream, " :%d", align);
1.2586 + func (stream, ", %s", arm_regnames[rm]);
1.2592 + int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
1.2593 + int rn = ((given >> 16) & 0xf);
1.2594 + int rm = ((given >> 0) & 0xf);
1.2595 + int align = ((given >> 4) & 0x1);
1.2596 + int size = ((given >> 6) & 0x3);
1.2597 + int type = ((given >> 8) & 0x3);
1.2599 + int stride = ((given >> 5) & 0x1);
1.2602 + if (stride && (n == 1))
1.2609 + for (ix = 0; ix != n; ix++)
1.2610 + func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
1.2612 + func (stream, "d%d[]", rd);
1.2614 + func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
1.2615 + func (stream, "}, [%s", arm_regnames[rn]);
1.2618 + align = (8 * (type + 1)) << size;
1.2620 + align = (size > 1) ? align >> 1 : align;
1.2621 + if (type == 2 || (type == 0 && !size))
1.2622 + func (stream, " :<bad align %d>", align);
1.2624 + func (stream, " :%d", align);
1.2630 + func (stream, ", %s", arm_regnames[rm]);
1.2636 + int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
1.2637 + int size = (given >> 20) & 3;
1.2638 + int reg = raw_reg & ((4 << size) - 1);
1.2639 + int ix = raw_reg >> size >> 2;
1.2641 + func (stream, "d%d[%d]", reg, ix);
1.2646 + /* Neon encoded constant for mov, mvn, vorr, vbic. */
1.2649 + int cmode = (given >> 8) & 0xf;
1.2650 + int op = (given >> 5) & 0x1;
1.2651 + unsigned long value = 0, hival = 0;
1.2656 + bits |= ((given >> 24) & 1) << 7;
1.2657 + bits |= ((given >> 16) & 7) << 4;
1.2658 + bits |= ((given >> 0) & 15) << 0;
1.2662 + shift = (cmode >> 1) & 3;
1.2663 + value = (unsigned long) bits << (8 * shift);
1.2668 + shift = (cmode >> 1) & 1;
1.2669 + value = (unsigned long) bits << (8 * shift);
1.2674 + shift = (cmode & 1) + 1;
1.2675 + value = (unsigned long) bits << (8 * shift);
1.2676 + value |= (1ul << (8 * shift)) - 1;
1.2679 + else if (cmode == 14)
1.2683 + /* Bit replication into bytes. */
1.2689 + for (ix = 7; ix >= 0; ix--)
1.2691 + mask = ((bits >> ix) & 1) ? 0xff : 0;
1.2693 + value = (value << 8) | mask;
1.2695 + hival = (hival << 8) | mask;
1.2701 + /* Byte replication. */
1.2702 + value = (unsigned long) bits;
1.2708 + /* Floating point encoding. */
1.2711 + value = (unsigned long) (bits & 0x7f) << 19;
1.2712 + value |= (unsigned long) (bits & 0x80) << 24;
1.2713 + tmp = bits & 0x40 ? 0x3c : 0x40;
1.2714 + value |= (unsigned long) tmp << 24;
1.2720 + func (stream, "<illegal constant %.8x:%x:%x>",
1.2728 + func (stream, "#%ld\t; 0x%.2lx", value, value);
1.2732 + func (stream, "#%ld\t; 0x%.4lx", value, value);
1.2738 + unsigned char valbytes[4];
1.2741 + /* Do this a byte at a time so we don't have to
1.2742 + worry about the host's endianness. */
1.2743 + valbytes[0] = value & 0xff;
1.2744 + valbytes[1] = (value >> 8) & 0xff;
1.2745 + valbytes[2] = (value >> 16) & 0xff;
1.2746 + valbytes[3] = (value >> 24) & 0xff;
1.2748 + floatformat_to_double
1.2749 + (& floatformat_ieee_single_little, valbytes,
1.2752 + func (stream, "#%.7g\t; 0x%.8lx", fvalue,
1.2756 + func (stream, "#%ld\t; 0x%.8lx",
1.2757 + (long) (((value & 0x80000000L) != 0)
1.2758 + ? value | ~0xffffffffL : value),
1.2763 + func (stream, "#0x%.8lx%.8lx", hival, value);
1.2774 + int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
1.2775 + int num = (given >> 8) & 0x3;
1.2778 + func (stream, "{d%d}", regno);
1.2779 + else if (num + regno >= 32)
1.2780 + func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
1.2782 + func (stream, "{d%d-d%d}", regno, regno + num);
1.2787 + case '0': case '1': case '2': case '3': case '4':
1.2788 + case '5': case '6': case '7': case '8': case '9':
1.2793 + c = arm_decode_bitfield (c, given, &value, &width);
1.2798 + func (stream, "%s", arm_regnames[value]);
1.2801 + func (stream, "%ld", value);
1.2802 + value_in_comment = value;
1.2805 + func (stream, "%ld", (1ul << width) - value);
1.2811 + /* Various width encodings. */
1.2813 + int base = 8 << (*c - 'S'); /* 8,16 or 32 */
1.2818 + if (*c >= '0' && *c <= '9')
1.2820 + else if (*c >= 'a' && *c <= 'f')
1.2821 + limit = *c - 'a' + 10;
1.2827 + if (value < low || value > high)
1.2828 + func (stream, "<illegal width %d>", base << value);
1.2830 + func (stream, "%d", base << value);
1.2834 + if (given & (1 << 6))
1.2838 + func (stream, "d%ld", value);
1.2843 + func (stream, "<illegal reg q%ld.5>", value >> 1);
1.2845 + func (stream, "q%ld", value >> 1);
1.2851 + func (stream, "%c", *c);
1.2855 + if (value == ((1ul << width) - 1))
1.2856 + func (stream, "%c", *c);
1.2859 + func (stream, "%c", c[(1 << width) - (int) value]);
1.2873 + func (stream, "%c", *c);
1.2876 + if (value_in_comment > 32 || value_in_comment < -16)
1.2877 + func (stream, "\t; 0x%lx", value_in_comment);
1.2885 +/* Return the name of a v7A special register. */
1.2888 +banked_regname (unsigned reg)
1.2892 + case 15: return "CPSR";
1.2893 + case 32: return "R8_usr";
1.2894 + case 33: return "R9_usr";
1.2895 + case 34: return "R10_usr";
1.2896 + case 35: return "R11_usr";
1.2897 + case 36: return "R12_usr";
1.2898 + case 37: return "SP_usr";
1.2899 + case 38: return "LR_usr";
1.2900 + case 40: return "R8_fiq";
1.2901 + case 41: return "R9_fiq";
1.2902 + case 42: return "R10_fiq";
1.2903 + case 43: return "R11_fiq";
1.2904 + case 44: return "R12_fiq";
1.2905 + case 45: return "SP_fiq";
1.2906 + case 46: return "LR_fiq";
1.2907 + case 48: return "LR_irq";
1.2908 + case 49: return "SP_irq";
1.2909 + case 50: return "LR_svc";
1.2910 + case 51: return "SP_svc";
1.2911 + case 52: return "LR_abt";
1.2912 + case 53: return "SP_abt";
1.2913 + case 54: return "LR_und";
1.2914 + case 55: return "SP_und";
1.2915 + case 60: return "LR_mon";
1.2916 + case 61: return "SP_mon";
1.2917 + case 62: return "ELR_hyp";
1.2918 + case 63: return "SP_hyp";
1.2919 + case 79: return "SPSR";
1.2920 + case 110: return "SPSR_fiq";
1.2921 + case 112: return "SPSR_irq";
1.2922 + case 114: return "SPSR_svc";
1.2923 + case 116: return "SPSR_abt";
1.2924 + case 118: return "SPSR_und";
1.2925 + case 124: return "SPSR_mon";
1.2926 + case 126: return "SPSR_hyp";
1.2927 + default: return NULL;
1.2931 +/* Print one ARM instruction from PC on INFO->STREAM. */
1.2934 +print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
1.2936 + const struct opcode32 *insn;
1.2937 + void *stream = info->stream;
1.2938 + fprintf_ftype func = info->fprintf_func;
1.2939 + struct arm_private_data *private_data = info->private_data;
1.2941 + if (print_insn_coprocessor (pc, info, given, FALSE))
1.2944 + if (print_insn_neon (info, given, FALSE))
1.2947 + for (insn = arm_opcodes; insn->assembler; insn++)
1.2949 + if ((given & insn->mask) != insn->value)
1.2952 + if ((insn->arch & private_data->features.core) == 0)
1.2955 + /* Special case: an instruction with all bits set in the condition field
1.2956 + (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
1.2957 + or by the catchall at the end of the table. */
1.2958 + if ((given & 0xF0000000) != 0xF0000000
1.2959 + || (insn->mask & 0xF0000000) == 0xF0000000
1.2960 + || (insn->mask == 0 && insn->value == 0))
1.2962 + unsigned long u_reg = 16;
1.2963 + unsigned long U_reg = 16;
1.2964 + bfd_boolean is_unpredictable = FALSE;
1.2965 + signed long value_in_comment = 0;
1.2968 + for (c = insn->assembler; *c; c++)
1.2972 + bfd_boolean allow_unpredictable = FALSE;
1.2981 + value_in_comment = print_arm_address (pc, info, given);
1.2985 + /* Set P address bit and use normal address
1.2987 + value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
1.2991 + allow_unpredictable = TRUE;
1.2993 + if ((given & 0x004f0000) == 0x004f0000)
1.2995 + /* PC relative with immediate offset. */
1.2996 + bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
1.3000 + /* Elide positive zero offset. */
1.3001 + if (offset || NEGATIVE_BIT_SET)
1.3002 + func (stream, "[pc, #%s%d]\t; ",
1.3003 + NEGATIVE_BIT_SET ? "-" : "", offset);
1.3005 + func (stream, "[pc]\t; ");
1.3006 + if (NEGATIVE_BIT_SET)
1.3008 + info->print_address_func (offset + pc + 8, info);
1.3012 + /* Always show the offset. */
1.3013 + func (stream, "[pc], #%s%d",
1.3014 + NEGATIVE_BIT_SET ? "-" : "", offset);
1.3015 + if (! allow_unpredictable)
1.3016 + is_unpredictable = TRUE;
1.3021 + int offset = ((given & 0xf00) >> 4) | (given & 0xf);
1.3024 + arm_regnames[(given >> 16) & 0xf]);
1.3028 + if (IMMEDIATE_BIT_SET)
1.3030 + /* Elide offset for non-writeback
1.3032 + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
1.3034 + func (stream, ", #%s%d",
1.3035 + NEGATIVE_BIT_SET ? "-" : "", offset);
1.3037 + if (NEGATIVE_BIT_SET)
1.3040 + value_in_comment = offset;
1.3044 + /* Register Offset or Register Pre-Indexed. */
1.3045 + func (stream, ", %s%s",
1.3046 + NEGATIVE_BIT_SET ? "-" : "",
1.3047 + arm_regnames[given & 0xf]);
1.3049 + /* Writing back to the register that is the source/
1.3050 + destination of the load/store is unpredictable. */
1.3051 + if (! allow_unpredictable
1.3053 + && ((given & 0xf) == ((given >> 12) & 0xf)))
1.3054 + is_unpredictable = TRUE;
1.3058 + WRITEBACK_BIT_SET ? "!" : "");
1.3062 + if (IMMEDIATE_BIT_SET)
1.3064 + /* Immediate Post-indexed. */
1.3065 + /* PR 10924: Offset must be printed, even if it is zero. */
1.3066 + func (stream, "], #%s%d",
1.3067 + NEGATIVE_BIT_SET ? "-" : "", offset);
1.3068 + if (NEGATIVE_BIT_SET)
1.3070 + value_in_comment = offset;
1.3074 + /* Register Post-indexed. */
1.3075 + func (stream, "], %s%s",
1.3076 + NEGATIVE_BIT_SET ? "-" : "",
1.3077 + arm_regnames[given & 0xf]);
1.3079 + /* Writing back to the register that is the source/
1.3080 + destination of the load/store is unpredictable. */
1.3081 + if (! allow_unpredictable
1.3082 + && (given & 0xf) == ((given >> 12) & 0xf))
1.3083 + is_unpredictable = TRUE;
1.3086 + if (! allow_unpredictable)
1.3088 + /* Writeback is automatically implied by post- addressing.
1.3089 + Setting the W bit is unnecessary and ARM specify it as
1.3090 + being unpredictable. */
1.3091 + if (WRITEBACK_BIT_SET
1.3092 + /* Specifying the PC register as the post-indexed
1.3093 + registers is also unpredictable. */
1.3094 + || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
1.3095 + is_unpredictable = TRUE;
1.3103 + bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
1.3104 + info->print_address_func (disp * 4 + pc + 8, info);
1.3109 + if (((given >> 28) & 0xf) != 0xe)
1.3111 + arm_conditional [(given >> 28) & 0xf]);
1.3120 + for (reg = 0; reg < 16; reg++)
1.3121 + if ((given & (1 << reg)) != 0)
1.3126 + func (stream, "%s", arm_regnames[reg]);
1.3130 + is_unpredictable = TRUE;
1.3135 + arm_decode_shift (given, func, stream, FALSE);
1.3139 + if ((given & 0x02000000) != 0)
1.3141 + int rotate = (given & 0xf00) >> 7;
1.3142 + int immed = (given & 0xff);
1.3144 + immed = (((immed << (32 - rotate))
1.3145 + | (immed >> rotate)) & 0xffffffff);
1.3146 + func (stream, "#%d", immed);
1.3147 + value_in_comment = immed;
1.3150 + arm_decode_shift (given, func, stream, TRUE);
1.3154 + if ((given & 0x0000f000) == 0x0000f000)
1.3156 + /* The p-variants of tst/cmp/cmn/teq are the pre-V6
1.3157 + mechanism for setting PSR flag bits. They are
1.3158 + obsolete in V6 onwards. */
1.3159 + if ((private_data->features.core & ARM_EXT_V6) == 0)
1.3165 + if ((given & 0x01200000) == 0x00200000)
1.3171 + int offset = given & 0xff;
1.3173 + value_in_comment = offset * 4;
1.3174 + if (NEGATIVE_BIT_SET)
1.3175 + value_in_comment = - value_in_comment;
1.3177 + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
1.3182 + func (stream, ", #%d]%s",
1.3184 + WRITEBACK_BIT_SET ? "!" : "");
1.3192 + if (WRITEBACK_BIT_SET)
1.3195 + func (stream, ", #%d", value_in_comment);
1.3199 + func (stream, ", {%d}", offset);
1.3200 + value_in_comment = offset;
1.3207 + /* Print ARM V5 BLX(1) address: pc+25 bits. */
1.3212 + if (! NEGATIVE_BIT_SET)
1.3213 + /* Is signed, hi bits should be ones. */
1.3214 + offset = (-1) ^ 0x00ffffff;
1.3216 + /* Offset is (SignExtend(offset field)<<2). */
1.3217 + offset += given & 0x00ffffff;
1.3219 + address = offset + pc + 8;
1.3221 + if (given & 0x01000000)
1.3222 + /* H bit allows addressing to 2-byte boundaries. */
1.3225 + info->print_address_func (address, info);
1.3230 + if ((given & 0x02000200) == 0x200)
1.3233 + unsigned sysm = (given & 0x004f0000) >> 16;
1.3235 + sysm |= (given & 0x300) >> 4;
1.3236 + name = banked_regname (sysm);
1.3239 + func (stream, "%s", name);
1.3241 + func (stream, "(UNDEF: %lu)", sysm);
1.3245 + func (stream, "%cPSR_",
1.3246 + (given & 0x00400000) ? 'S' : 'C');
1.3259 + if ((given & 0xf0) == 0x60)
1.3263 + case 0xf: func (stream, "sy"); break;
1.3265 + func (stream, "#%d", (int) given & 0xf);
1.3273 + case 0xf: func (stream, "sy"); break;
1.3274 + case 0x7: func (stream, "un"); break;
1.3275 + case 0xe: func (stream, "st"); break;
1.3276 + case 0x6: func (stream, "unst"); break;
1.3277 + case 0xb: func (stream, "ish"); break;
1.3278 + case 0xa: func (stream, "ishst"); break;
1.3279 + case 0x3: func (stream, "osh"); break;
1.3280 + case 0x2: func (stream, "oshst"); break;
1.3282 + func (stream, "#%d", (int) given & 0xf);
1.3288 + case '0': case '1': case '2': case '3': case '4':
1.3289 + case '5': case '6': case '7': case '8': case '9':
1.3294 + c = arm_decode_bitfield (c, given, &value, &width);
1.3300 + is_unpredictable = TRUE;
1.3305 + /* Eat the 'u' character. */
1.3309 + is_unpredictable = TRUE;
1.3314 + /* Eat the 'U' character. */
1.3318 + is_unpredictable = TRUE;
1.3321 + func (stream, "%s", arm_regnames[value]);
1.3324 + func (stream, "%ld", value);
1.3325 + value_in_comment = value;
1.3328 + func (stream, "%ld", value * 8);
1.3329 + value_in_comment = value * 8;
1.3332 + func (stream, "%ld", value + 1);
1.3333 + value_in_comment = value + 1;
1.3336 + func (stream, "0x%08lx", value);
1.3338 + /* Some SWI instructions have special
1.3340 + if ((given & 0x0fffffff) == 0x0FF00000)
1.3341 + func (stream, "\t; IMB");
1.3342 + else if ((given & 0x0fffffff) == 0x0FF00001)
1.3343 + func (stream, "\t; IMBRange");
1.3346 + func (stream, "%01lx", value & 0xf);
1.3347 + value_in_comment = value;
1.3352 + func (stream, "%c", *c);
1.3356 + if (value == ((1ul << width) - 1))
1.3357 + func (stream, "%c", *c);
1.3360 + func (stream, "%c", c[(1 << width) - (int) value]);
1.3372 + imm = (given & 0xf) | ((given & 0xfff00) >> 4);
1.3373 + func (stream, "%d", imm);
1.3374 + value_in_comment = imm;
1.3379 + /* LSB and WIDTH fields of BFI or BFC. The machine-
1.3380 + language instruction encodes LSB and MSB. */
1.3382 + long msb = (given & 0x001f0000) >> 16;
1.3383 + long lsb = (given & 0x00000f80) >> 7;
1.3384 + long w = msb - lsb + 1;
1.3387 + func (stream, "#%lu, #%lu", lsb, w);
1.3389 + func (stream, "(invalid: %lu:%lu)", lsb, msb);
1.3394 + /* Get the PSR/banked register name. */
1.3397 + unsigned sysm = (given & 0x004f0000) >> 16;
1.3399 + sysm |= (given & 0x300) >> 4;
1.3400 + name = banked_regname (sysm);
1.3403 + func (stream, "%s", name);
1.3405 + func (stream, "(UNDEF: %lu)", sysm);
1.3410 + /* 16-bit unsigned immediate from a MOVT or MOVW
1.3411 + instruction, encoded in bits 0:11 and 15:19. */
1.3413 + long hi = (given & 0x000f0000) >> 4;
1.3414 + long lo = (given & 0x00000fff);
1.3415 + long imm16 = hi | lo;
1.3417 + func (stream, "#%lu", imm16);
1.3418 + value_in_comment = imm16;
1.3428 + func (stream, "%c", *c);
1.3431 + if (value_in_comment > 32 || value_in_comment < -16)
1.3432 + func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
1.3434 + if (is_unpredictable)
1.3435 + func (stream, UNPREDICTABLE_INSTRUCTION);
1.3443 +/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
1.3446 +print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
1.3448 + const struct opcode16 *insn;
1.3449 + void *stream = info->stream;
1.3450 + fprintf_ftype func = info->fprintf_func;
1.3452 + for (insn = thumb_opcodes; insn->assembler; insn++)
1.3453 + if ((given & insn->mask) == insn->value)
1.3455 + signed long value_in_comment = 0;
1.3456 + const char *c = insn->assembler;
1.3465 + func (stream, "%c", *c);
1.3477 + func (stream, "%s", arm_conditional[IFTHEN_COND]);
1.3482 + func (stream, "%s", arm_conditional[IFTHEN_COND]);
1.3491 + ifthen_next_state = given & 0xff;
1.3492 + for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
1.3493 + func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
1.3494 + func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
1.3499 + if (ifthen_next_state)
1.3500 + func (stream, "\t; unpredictable branch in IT block\n");
1.3505 + func (stream, "\t; unpredictable <IT:%s>",
1.3506 + arm_conditional[IFTHEN_COND]);
1.3513 + reg = (given >> 3) & 0x7;
1.3514 + if (given & (1 << 6))
1.3517 + func (stream, "%s", arm_regnames[reg]);
1.3526 + if (given & (1 << 7))
1.3529 + func (stream, "%s", arm_regnames[reg]);
1.3534 + if (given & (1 << 8))
1.3538 + if (*c == 'O' && (given & (1 << 8)))
1.3548 + /* It would be nice if we could spot
1.3549 + ranges, and generate the rS-rE format: */
1.3550 + for (reg = 0; (reg < 8); reg++)
1.3551 + if ((given & (1 << reg)) != 0)
1.3556 + func (stream, "%s", arm_regnames[reg]);
1.3564 + func (stream, arm_regnames[14] /* "lr" */);
1.3571 + func (stream, arm_regnames[15] /* "pc" */);
1.3579 + /* Print writeback indicator for a LDMIA. We are doing a
1.3580 + writeback if the base register is not in the register
1.3582 + if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
1.3587 + /* Print ARM V6T2 CZB address: pc+4+6 bits. */
1.3589 + bfd_vma address = (pc + 4
1.3590 + + ((given & 0x00f8) >> 2)
1.3591 + + ((given & 0x0200) >> 3));
1.3592 + info->print_address_func (address, info);
1.3597 + /* Right shift immediate -- bits 6..10; 1-31 print
1.3598 + as themselves, 0 prints as 32. */
1.3600 + long imm = (given & 0x07c0) >> 6;
1.3603 + func (stream, "#%ld", imm);
1.3607 + case '0': case '1': case '2': case '3': case '4':
1.3608 + case '5': case '6': case '7': case '8': case '9':
1.3610 + int bitstart = *c++ - '0';
1.3613 + while (*c >= '0' && *c <= '9')
1.3614 + bitstart = (bitstart * 10) + *c++ - '0';
1.3623 + while (*c >= '0' && *c <= '9')
1.3624 + bitend = (bitend * 10) + *c++ - '0';
1.3627 + reg = given >> bitstart;
1.3628 + reg &= (2 << (bitend - bitstart)) - 1;
1.3633 + func (stream, "%s", arm_regnames[reg]);
1.3637 + func (stream, "%ld", reg);
1.3638 + value_in_comment = reg;
1.3642 + func (stream, "%ld", reg << 1);
1.3643 + value_in_comment = reg << 1;
1.3647 + func (stream, "%ld", reg << 2);
1.3648 + value_in_comment = reg << 2;
1.3652 + /* PC-relative address -- the bottom two
1.3653 + bits of the address are dropped
1.3654 + before the calculation. */
1.3655 + info->print_address_func
1.3656 + (((pc + 4) & ~3) + (reg << 2), info);
1.3657 + value_in_comment = 0;
1.3661 + func (stream, "0x%04lx", reg);
1.3665 + reg = ((reg ^ (1 << bitend)) - (1 << bitend));
1.3666 + info->print_address_func (reg * 2 + pc + 4, info);
1.3667 + value_in_comment = 0;
1.3671 + func (stream, "%s", arm_conditional [reg]);
1.3682 + if ((given & (1 << bitstart)) != 0)
1.3683 + func (stream, "%c", *c);
1.3688 + if ((given & (1 << bitstart)) != 0)
1.3689 + func (stream, "%c", *c++);
1.3691 + func (stream, "%c", *++c);
1.3705 + if (value_in_comment > 32 || value_in_comment < -16)
1.3706 + func (stream, "\t; 0x%lx", value_in_comment);
1.3714 +/* Return the name of an V7M special register. */
1.3721 + case 0: return "APSR";
1.3722 + case 1: return "IAPSR";
1.3723 + case 2: return "EAPSR";
1.3724 + case 3: return "PSR";
1.3725 + case 5: return "IPSR";
1.3726 + case 6: return "EPSR";
1.3727 + case 7: return "IEPSR";
1.3728 + case 8: return "MSP";
1.3729 + case 9: return "PSP";
1.3730 + case 16: return "PRIMASK";
1.3731 + case 17: return "BASEPRI";
1.3732 + case 18: return "BASEPRI_MAX";
1.3733 + case 19: return "FAULTMASK";
1.3734 + case 20: return "CONTROL";
1.3735 + default: return "<unknown>";
1.3739 +/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
1.3742 +print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
1.3744 + const struct opcode32 *insn;
1.3745 + void *stream = info->stream;
1.3746 + fprintf_ftype func = info->fprintf_func;
1.3748 + if (print_insn_coprocessor (pc, info, given, TRUE))
1.3751 + if (print_insn_neon (info, given, TRUE))
1.3754 + for (insn = thumb32_opcodes; insn->assembler; insn++)
1.3755 + if ((given & insn->mask) == insn->value)
1.3757 + bfd_boolean is_unpredictable = FALSE;
1.3758 + signed long value_in_comment = 0;
1.3759 + const char *c = insn->assembler;
1.3765 + func (stream, "%c", *c);
1.3777 + func (stream, "%s", arm_conditional[IFTHEN_COND]);
1.3781 + if (ifthen_next_state)
1.3782 + func (stream, "\t; unpredictable branch in IT block\n");
1.3787 + func (stream, "\t; unpredictable <IT:%s>",
1.3788 + arm_conditional[IFTHEN_COND]);
1.3793 + unsigned int imm12 = 0;
1.3795 + imm12 |= (given & 0x000000ffu);
1.3796 + imm12 |= (given & 0x00007000u) >> 4;
1.3797 + imm12 |= (given & 0x04000000u) >> 15;
1.3798 + func (stream, "#%u", imm12);
1.3799 + value_in_comment = imm12;
1.3805 + unsigned int bits = 0, imm, imm8, mod;
1.3807 + bits |= (given & 0x000000ffu);
1.3808 + bits |= (given & 0x00007000u) >> 4;
1.3809 + bits |= (given & 0x04000000u) >> 15;
1.3810 + imm8 = (bits & 0x0ff);
1.3811 + mod = (bits & 0xf00) >> 8;
1.3814 + case 0: imm = imm8; break;
1.3815 + case 1: imm = ((imm8 << 16) | imm8); break;
1.3816 + case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
1.3817 + case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
1.3819 + mod = (bits & 0xf80) >> 7;
1.3820 + imm8 = (bits & 0x07f) | 0x80;
1.3821 + imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
1.3823 + func (stream, "#%u", imm);
1.3824 + value_in_comment = imm;
1.3830 + unsigned int imm = 0;
1.3832 + imm |= (given & 0x000000ffu);
1.3833 + imm |= (given & 0x00007000u) >> 4;
1.3834 + imm |= (given & 0x04000000u) >> 15;
1.3835 + imm |= (given & 0x000f0000u) >> 4;
1.3836 + func (stream, "#%u", imm);
1.3837 + value_in_comment = imm;
1.3843 + unsigned int imm = 0;
1.3845 + imm |= (given & 0x000f0000u) >> 16;
1.3846 + imm |= (given & 0x00000ff0u) >> 0;
1.3847 + imm |= (given & 0x0000000fu) << 12;
1.3848 + func (stream, "#%u", imm);
1.3849 + value_in_comment = imm;
1.3855 + unsigned int imm = 0;
1.3857 + imm |= (given & 0x00000fffu);
1.3858 + imm |= (given & 0x000f0000u) >> 4;
1.3859 + func (stream, "#%u", imm);
1.3860 + value_in_comment = imm;
1.3866 + unsigned int reg = (given & 0x0000000fu);
1.3867 + unsigned int stp = (given & 0x00000030u) >> 4;
1.3868 + unsigned int imm = 0;
1.3869 + imm |= (given & 0x000000c0u) >> 6;
1.3870 + imm |= (given & 0x00007000u) >> 10;
1.3872 + func (stream, "%s", arm_regnames[reg]);
1.3877 + func (stream, ", lsl #%u", imm);
1.3883 + func (stream, ", lsr #%u", imm);
1.3889 + func (stream, ", asr #%u", imm);
1.3894 + func (stream, ", rrx");
1.3896 + func (stream, ", ror #%u", imm);
1.3903 + unsigned int Rn = (given & 0x000f0000) >> 16;
1.3904 + unsigned int U = ! NEGATIVE_BIT_SET;
1.3905 + unsigned int op = (given & 0x00000f00) >> 8;
1.3906 + unsigned int i12 = (given & 0x00000fff);
1.3907 + unsigned int i8 = (given & 0x000000ff);
1.3908 + bfd_boolean writeback = FALSE, postind = FALSE;
1.3911 + func (stream, "[%s", arm_regnames[Rn]);
1.3912 + if (U) /* 12-bit positive immediate offset. */
1.3916 + value_in_comment = offset;
1.3918 + else if (Rn == 15) /* 12-bit negative immediate offset. */
1.3919 + offset = - (int) i12;
1.3920 + else if (op == 0x0) /* Shifted register offset. */
1.3922 + unsigned int Rm = (i8 & 0x0f);
1.3923 + unsigned int sh = (i8 & 0x30) >> 4;
1.3925 + func (stream, ", %s", arm_regnames[Rm]);
1.3927 + func (stream, ", lsl #%u", sh);
1.3933 + case 0xE: /* 8-bit positive immediate offset. */
1.3937 + case 0xC: /* 8-bit negative immediate offset. */
1.3941 + case 0xF: /* 8-bit + preindex with wb. */
1.3946 + case 0xD: /* 8-bit - preindex with wb. */
1.3951 + case 0xB: /* 8-bit + postindex. */
1.3956 + case 0x9: /* 8-bit - postindex. */
1.3962 + func (stream, ", <undefined>]");
1.3967 + func (stream, "], #%d", offset);
1.3971 + func (stream, ", #%d", offset);
1.3972 + func (stream, writeback ? "]!" : "]");
1.3977 + func (stream, "\t; ");
1.3978 + info->print_address_func (((pc + 4) & ~3) + offset, info);
1.3986 + unsigned int U = ! NEGATIVE_BIT_SET;
1.3987 + unsigned int W = WRITEBACK_BIT_SET;
1.3988 + unsigned int Rn = (given & 0x000f0000) >> 16;
1.3989 + unsigned int off = (given & 0x000000ff);
1.3991 + func (stream, "[%s", arm_regnames[Rn]);
1.3997 + func (stream, ", #%c%u", U ? '+' : '-', off * 4);
1.3998 + value_in_comment = off * 4 * U ? 1 : -1;
1.4006 + func (stream, "], ");
1.4009 + func (stream, "#%c%u", U ? '+' : '-', off * 4);
1.4010 + value_in_comment = off * 4 * U ? 1 : -1;
1.4014 + func (stream, "{%u}", off);
1.4015 + value_in_comment = off;
1.4023 + unsigned int Sbit = (given & 0x01000000) >> 24;
1.4024 + unsigned int type = (given & 0x00600000) >> 21;
1.4028 + case 0: func (stream, Sbit ? "sb" : "b"); break;
1.4029 + case 1: func (stream, Sbit ? "sh" : "h"); break;
1.4047 + for (reg = 0; reg < 16; reg++)
1.4048 + if ((given & (1 << reg)) != 0)
1.4053 + func (stream, "%s", arm_regnames[reg]);
1.4061 + unsigned int msb = (given & 0x0000001f);
1.4062 + unsigned int lsb = 0;
1.4064 + lsb |= (given & 0x000000c0u) >> 6;
1.4065 + lsb |= (given & 0x00007000u) >> 10;
1.4066 + func (stream, "#%u, #%u", lsb, msb - lsb + 1);
1.4072 + unsigned int width = (given & 0x0000001f) + 1;
1.4073 + unsigned int lsb = 0;
1.4075 + lsb |= (given & 0x000000c0u) >> 6;
1.4076 + lsb |= (given & 0x00007000u) >> 10;
1.4077 + func (stream, "#%u, #%u", lsb, width);
1.4083 + unsigned int S = (given & 0x04000000u) >> 26;
1.4084 + unsigned int J1 = (given & 0x00002000u) >> 13;
1.4085 + unsigned int J2 = (given & 0x00000800u) >> 11;
1.4091 + offset |= (given & 0x003f0000) >> 4;
1.4092 + offset |= (given & 0x000007ff) << 1;
1.4095 + info->print_address_func (pc + 4 + offset, info);
1.4101 + unsigned int S = (given & 0x04000000u) >> 26;
1.4102 + unsigned int I1 = (given & 0x00002000u) >> 13;
1.4103 + unsigned int I2 = (given & 0x00000800u) >> 11;
1.4107 + offset |= !(I1 ^ S) << 23;
1.4108 + offset |= !(I2 ^ S) << 22;
1.4109 + offset |= (given & 0x03ff0000u) >> 4;
1.4110 + offset |= (given & 0x000007ffu) << 1;
1.4114 + /* BLX target addresses are always word aligned. */
1.4115 + if ((given & 0x00001000u) == 0)
1.4118 + info->print_address_func (offset, info);
1.4124 + unsigned int shift = 0;
1.4126 + shift |= (given & 0x000000c0u) >> 6;
1.4127 + shift |= (given & 0x00007000u) >> 10;
1.4128 + if (WRITEBACK_BIT_SET)
1.4129 + func (stream, ", asr #%u", shift);
1.4131 + func (stream, ", lsl #%u", shift);
1.4132 + /* else print nothing - lsl #0 */
1.4138 + unsigned int rot = (given & 0x00000030) >> 4;
1.4141 + func (stream, ", ror #%u", rot * 8);
1.4146 + if ((given & 0xf0) == 0x60)
1.4150 + case 0xf: func (stream, "sy"); break;
1.4152 + func (stream, "#%d", (int) given & 0xf);
1.4160 + case 0xf: func (stream, "sy"); break;
1.4161 + case 0x7: func (stream, "un"); break;
1.4162 + case 0xe: func (stream, "st"); break;
1.4163 + case 0x6: func (stream, "unst"); break;
1.4164 + case 0xb: func (stream, "ish"); break;
1.4165 + case 0xa: func (stream, "ishst"); break;
1.4166 + case 0x3: func (stream, "osh"); break;
1.4167 + case 0x2: func (stream, "oshst"); break;
1.4169 + func (stream, "#%d", (int) given & 0xf);
1.4176 + if ((given & 0xff) == 0)
1.4178 + func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
1.4188 + else if ((given & 0x20) == 0x20)
1.4191 + unsigned sysm = (given & 0xf00) >> 8;
1.4193 + sysm |= (given & 0x30);
1.4194 + sysm |= (given & 0x00100000) >> 14;
1.4195 + name = banked_regname (sysm);
1.4198 + func (stream, "%s", name);
1.4200 + func (stream, "(UNDEF: %lu)", sysm);
1.4204 + func (stream, psr_name (given & 0xff));
1.4209 + if (((given & 0xff) == 0)
1.4210 + || ((given & 0x20) == 0x20))
1.4213 + unsigned sm = (given & 0xf0000) >> 16;
1.4215 + sm |= (given & 0x30);
1.4216 + sm |= (given & 0x00100000) >> 14;
1.4217 + name = banked_regname (sm);
1.4220 + func (stream, "%s", name);
1.4222 + func (stream, "(UNDEF: %lu)", sm);
1.4225 + func (stream, psr_name (given & 0xff));
1.4228 + case '0': case '1': case '2': case '3': case '4':
1.4229 + case '5': case '6': case '7': case '8': case '9':
1.4234 + c = arm_decode_bitfield (c, given, &val, &width);
1.4239 + func (stream, "%lu", val);
1.4240 + value_in_comment = val;
1.4244 + func (stream, "%lu", val * 4);
1.4245 + value_in_comment = val * 4;
1.4250 + is_unpredictable = TRUE;
1.4253 + func (stream, "%s", arm_regnames[val]);
1.4257 + func (stream, "%s", arm_conditional[val]);
1.4262 + if (val == ((1ul << width) - 1))
1.4263 + func (stream, "%c", *c);
1.4269 + func (stream, "%c", *c);
1.4273 + func (stream, "%c", c[(1 << width) - (int) val]);
1.4278 + func (stream, "0x%lx", val & 0xffffffffUL);
1.4289 + If we have a PC relative offset in an LDRD or STRD
1.4290 + instructions then display the decoded address. */
1.4291 + if (((given >> 16) & 0xf) == 0xf)
1.4293 + bfd_vma offset = (given & 0xff) * 4;
1.4295 + if ((given & (1 << 23)) == 0)
1.4297 + func (stream, "\t; ");
1.4298 + info->print_address_func ((pc & ~3) + 4 + offset, info);
1.4307 + if (value_in_comment > 32 || value_in_comment < -16)
1.4308 + func (stream, "\t; 0x%lx", value_in_comment);
1.4310 + if (is_unpredictable)
1.4311 + func (stream, UNPREDICTABLE_INSTRUCTION);
1.4320 +/* Print data bytes on INFO->STREAM. */
1.4323 +print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
1.4324 + struct disassemble_info *info,
1.4327 + switch (info->bytes_per_chunk)
1.4330 + info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
1.4333 + info->fprintf_func (info->stream, ".short\t0x%04lx", given);
1.4336 + info->fprintf_func (info->stream, ".word\t0x%08lx", given);
1.4343 +/* Disallow mapping symbols ($a, $b, $d, $t etc) from
1.4344 + being displayed in symbol relative addresses. */
1.4347 +arm_symbol_is_valid (asymbol * sym,
1.4348 + struct disassemble_info * info ATTRIBUTE_UNUSED)
1.4355 + name = bfd_asymbol_name (sym);
1.4357 + return (name && *name != '$');
1.4360 +/* Parse an individual disassembler option. */
1.4363 +parse_arm_disassembler_option (char *option)
1.4368 + if (CONST_STRNEQ (option, "reg-names-"))
1.4374 + for (i = NUM_ARM_REGNAMES; i--;)
1.4375 + if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
1.4377 + regname_selected = i;
1.4382 + /* XXX - should break 'option' at following delimiter. */
1.4383 + fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
1.4385 + else if (CONST_STRNEQ (option, "force-thumb"))
1.4387 + else if (CONST_STRNEQ (option, "no-force-thumb"))
1.4390 + /* XXX - should break 'option' at following delimiter. */
1.4391 + fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
1.4396 +/* Parse the string of disassembler options, spliting it at whitespaces
1.4397 + or commas. (Whitespace separators supported for backwards compatibility). */
1.4400 +parse_disassembler_options (char *options)
1.4407 + parse_arm_disassembler_option (options);
1.4409 + /* Skip forward to next seperator. */
1.4410 + while ((*options) && (! ISSPACE (*options)) && (*options != ','))
1.4412 + /* Skip forward past seperators. */
1.4413 + while (ISSPACE (*options) || (*options == ','))
1.4418 +/* Search back through the insn stream to determine if this instruction is
1.4419 + conditionally executed. */
1.4422 +find_ifthen_state (bfd_vma pc,
1.4423 + struct disassemble_info *info,
1.4429 + /* COUNT is twice the number of instructions seen. It will be odd if we
1.4430 + just crossed an instruction boundary. */
1.4433 + unsigned int seen_it;
1.4443 + /* Scan backwards looking for IT instructions, keeping track of where
1.4444 + instruction boundaries are. We don't know if something is actually an
1.4445 + IT instruction until we find a definite instruction boundary. */
1.4448 + if (addr == 0 || info->symbol_at_address_func (addr, info))
1.4450 + /* A symbol must be on an instruction boundary, and will not
1.4451 + be within an IT block. */
1.4452 + if (seen_it && (count & 1))
1.4458 + status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
1.4463 + insn = (b[0]) | (b[1] << 8);
1.4465 + insn = (b[1]) | (b[0] << 8);
1.4468 + if ((insn & 0xf800) < 0xe800)
1.4470 + /* Addr + 2 is an instruction boundary. See if this matches
1.4471 + the expected boundary based on the position of the last
1.4478 + if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
1.4480 + /* This could be an IT instruction. */
1.4482 + it_count = count >> 1;
1.4484 + if ((insn & 0xf800) >= 0xe800)
1.4487 + count = (count + 2) | 1;
1.4488 + /* IT blocks contain at most 4 instructions. */
1.4489 + if (count >= 8 && !seen_it)
1.4492 + /* We found an IT instruction. */
1.4493 + ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
1.4494 + if ((ifthen_state & 0xf) == 0)
1.4498 +/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
1.4502 +is_mapping_symbol (struct disassemble_info *info, int n,
1.4503 + enum map_type *map_type)
1.4507 + name = bfd_asymbol_name (info->symtab[n]);
1.4508 + if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
1.4509 + && (name[2] == 0 || name[2] == '.'))
1.4511 + *map_type = ((name[1] == 'a') ? MAP_ARM
1.4512 + : (name[1] == 't') ? MAP_THUMB
1.4520 +/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
1.4521 + Returns nonzero if *MAP_TYPE was set. */
1.4524 +get_map_sym_type (struct disassemble_info *info,
1.4526 + enum map_type *map_type)
1.4528 + /* If the symbol is in a different section, ignore it. */
1.4529 + if (info->section != NULL && info->section != info->symtab[n]->section)
1.4532 + return is_mapping_symbol (info, n, map_type);
1.4535 +/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
1.4536 + Returns nonzero if *MAP_TYPE was set. */
1.4539 +get_sym_code_type (struct disassemble_info *info,
1.4541 + enum map_type *map_type)
1.4547 + /* If the symbol is in a different section, ignore it. */
1.4548 + if (info->section != NULL && info->section != info->symtab[n]->section)
1.4551 + es = *(elf_symbol_type **)(info->symtab + n);
1.4552 + type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
1.4554 + /* If the symbol has function type then use that. */
1.4555 + if (type == STT_FUNC || type == STT_GNU_IFUNC)
1.4557 + if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
1.4558 + *map_type = MAP_THUMB;
1.4567 +/* Given a bfd_mach_arm_XXX value, this function fills in the fields
1.4568 + of the supplied arm_feature_set structure with bitmasks indicating
1.4569 + the support base architectures and coprocessor extensions.
1.4571 + FIXME: This could more efficiently implemented as a constant array,
1.4572 + although it would also be less robust. */
1.4575 +select_arm_features (unsigned long mach,
1.4576 + arm_feature_set * features)
1.4579 +#define ARM_FEATURE(ARCH,CEXT) \
1.4580 + features->core = (ARCH); \
1.4581 + features->coproc = (CEXT) | FPU_FPA; \
1.4586 + case bfd_mach_arm_2: ARM_ARCH_V2;
1.4587 + case bfd_mach_arm_2a: ARM_ARCH_V2S;
1.4588 + case bfd_mach_arm_3: ARM_ARCH_V3;
1.4589 + case bfd_mach_arm_3M: ARM_ARCH_V3M;
1.4590 + case bfd_mach_arm_4: ARM_ARCH_V4;
1.4591 + case bfd_mach_arm_4T: ARM_ARCH_V4T;
1.4592 + case bfd_mach_arm_5: ARM_ARCH_V5;
1.4593 + case bfd_mach_arm_5T: ARM_ARCH_V5T;
1.4594 + case bfd_mach_arm_5TE: ARM_ARCH_V5TE;
1.4595 + case bfd_mach_arm_XScale: ARM_ARCH_XSCALE;
1.4596 + case bfd_mach_arm_ep9312: ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK);
1.4597 + case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT;
1.4598 + case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
1.4599 + /* If the machine type is unknown allow all
1.4600 + architecture types and all extensions. */
1.4601 + case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL);
1.4608 +/* NOTE: There are no checks in these routines that
1.4609 + the relevant number of data bytes exist. */
1.4612 +print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
1.4617 + int is_thumb = FALSE;
1.4620 + unsigned int size = 4;
1.4621 + void (*printer) (bfd_vma, struct disassemble_info *, long);
1.4622 + bfd_boolean found = FALSE;
1.4623 + struct arm_private_data *private_data;
1.4625 + if (info->disassembler_options)
1.4627 + parse_disassembler_options (info->disassembler_options);
1.4629 + /* To avoid repeated parsing of these options, we remove them here. */
1.4630 + info->disassembler_options = NULL;
1.4633 + /* PR 10288: Control which instructions will be disassembled. */
1.4634 + if (info->private_data == NULL)
1.4636 + static struct arm_private_data private;
1.4638 + if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
1.4639 + /* If the user did not use the -m command line switch then default to
1.4640 + disassembling all types of ARM instruction.
1.4642 + The info->mach value has to be ignored as this will be based on
1.4643 + the default archictecture for the target and/or hints in the notes
1.4644 + section, but it will never be greater than the current largest arm
1.4645 + machine value (iWMMXt2), which is only equivalent to the V5TE
1.4646 + architecture. ARM architectures have advanced beyond the machine
1.4647 + value encoding, and these newer architectures would be ignored if
1.4648 + the machine value was used.
1.4650 + Ie the -m switch is used to restrict which instructions will be
1.4651 + disassembled. If it is necessary to use the -m switch to tell
1.4652 + objdump that an ARM binary is being disassembled, eg because the
1.4653 + input is a raw binary file, but it is also desired to disassemble
1.4654 + all ARM instructions then use "-marm". This will select the
1.4655 + "unknown" arm architecture which is compatible with any ARM
1.4657 + info->mach = bfd_mach_arm_unknown;
1.4659 + /* Compute the architecture bitmask from the machine number.
1.4660 + Note: This assumes that the machine number will not change
1.4661 + during disassembly.... */
1.4662 + select_arm_features (info->mach, & private.features);
1.4664 + private.has_mapping_symbols = -1;
1.4665 + private.last_mapping_sym = -1;
1.4666 + private.last_mapping_addr = 0;
1.4668 + info->private_data = & private;
1.4671 + private_data = info->private_data;
1.4673 + /* Decide if our code is going to be little-endian, despite what the
1.4674 + function argument might say. */
1.4675 + little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
1.4677 + /* For ELF, consult the symbol table to determine what kind of code
1.4679 + if (info->symtab_size != 0
1.4680 + && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
1.4685 + enum map_type type = MAP_ARM;
1.4687 + /* Start scanning at the start of the function, or wherever
1.4688 + we finished last time. */
1.4689 + start = info->symtab_pos + 1;
1.4690 + if (start < private_data->last_mapping_sym)
1.4691 + start = private_data->last_mapping_sym;
1.4694 + /* First, look for mapping symbols. */
1.4695 + if (private_data->has_mapping_symbols != 0)
1.4697 + /* Scan up to the location being disassembled. */
1.4698 + for (n = start; n < info->symtab_size; n++)
1.4700 + addr = bfd_asymbol_value (info->symtab[n]);
1.4703 + if (get_map_sym_type (info, n, &type))
1.4712 + /* No mapping symbol found at this address. Look backwards
1.4713 + for a preceding one. */
1.4714 + for (n = start - 1; n >= 0; n--)
1.4716 + if (get_map_sym_type (info, n, &type))
1.4726 + private_data->has_mapping_symbols = 1;
1.4728 + /* No mapping symbols were found. A leading $d may be
1.4729 + omitted for sections which start with data; but for
1.4730 + compatibility with legacy and stripped binaries, only
1.4731 + assume the leading $d if there is at least one mapping
1.4732 + symbol in the file. */
1.4733 + if (!found && private_data->has_mapping_symbols == -1)
1.4735 + /* Look for mapping symbols, in any section. */
1.4736 + for (n = 0; n < info->symtab_size; n++)
1.4737 + if (is_mapping_symbol (info, n, &type))
1.4739 + private_data->has_mapping_symbols = 1;
1.4742 + if (private_data->has_mapping_symbols == -1)
1.4743 + private_data->has_mapping_symbols = 0;
1.4746 + if (!found && private_data->has_mapping_symbols == 1)
1.4753 + /* Next search for function symbols to separate ARM from Thumb
1.4754 + in binaries without mapping symbols. */
1.4757 + /* Scan up to the location being disassembled. */
1.4758 + for (n = start; n < info->symtab_size; n++)
1.4760 + addr = bfd_asymbol_value (info->symtab[n]);
1.4763 + if (get_sym_code_type (info, n, &type))
1.4772 + /* No mapping symbol found at this address. Look backwards
1.4773 + for a preceding one. */
1.4774 + for (n = start - 1; n >= 0; n--)
1.4776 + if (get_sym_code_type (info, n, &type))
1.4786 + private_data->last_mapping_sym = last_sym;
1.4787 + private_data->last_type = type;
1.4788 + is_thumb = (private_data->last_type == MAP_THUMB);
1.4789 + is_data = (private_data->last_type == MAP_DATA);
1.4791 + /* Look a little bit ahead to see if we should print out
1.4792 + two or four bytes of data. If there's a symbol,
1.4793 + mapping or otherwise, after two bytes then don't
1.4798 + for (n = last_sym + 1; n < info->symtab_size; n++)
1.4800 + addr = bfd_asymbol_value (info->symtab[n]);
1.4802 + && (info->section == NULL
1.4803 + || info->section == info->symtab[n]->section))
1.4805 + if (addr - pc < size)
1.4810 + /* If the next symbol is after three bytes, we need to
1.4811 + print only part of the data, so that we can use either
1.4814 + size = (pc & 1) ? 1 : 2;
1.4819 + if (info->symbols != NULL)
1.4821 + if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
1.4823 + coff_symbol_type * cs;
1.4825 + cs = coffsymbol (*info->symbols);
1.4826 + is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
1.4827 + || cs->native->u.syment.n_sclass == C_THUMBSTAT
1.4828 + || cs->native->u.syment.n_sclass == C_THUMBLABEL
1.4829 + || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
1.4830 + || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
1.4832 + else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
1.4835 + /* If no mapping symbol has been found then fall back to the type
1.4836 + of the function symbol. */
1.4837 + elf_symbol_type * es;
1.4840 + es = *(elf_symbol_type **)(info->symbols);
1.4841 + type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
1.4843 + is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
1.4844 + == ST_BRANCH_TO_THUMB)
1.4845 + || type == STT_ARM_16BIT);
1.4853 + info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
1.4855 + info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
1.4857 + info->bytes_per_line = 4;
1.4859 + /* PR 10263: Disassemble data if requested to do so by the user. */
1.4860 + if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
1.4864 + /* Size was already set above. */
1.4865 + info->bytes_per_chunk = size;
1.4866 + printer = print_insn_data;
1.4868 + status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
1.4871 + for (i = size - 1; i >= 0; i--)
1.4872 + given = b[i] | (given << 8);
1.4874 + for (i = 0; i < (int) size; i++)
1.4875 + given = b[i] | (given << 8);
1.4879 + /* In ARM mode endianness is a straightforward issue: the instruction
1.4880 + is four bytes long and is either ordered 0123 or 3210. */
1.4881 + printer = print_insn_arm;
1.4882 + info->bytes_per_chunk = 4;
1.4885 + status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
1.4887 + given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
1.4889 + given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
1.4893 + /* In Thumb mode we have the additional wrinkle of two
1.4894 + instruction lengths. Fortunately, the bits that determine
1.4895 + the length of the current instruction are always to be found
1.4896 + in the first two bytes. */
1.4897 + printer = print_insn_thumb16;
1.4898 + info->bytes_per_chunk = 2;
1.4901 + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
1.4903 + given = (b[0]) | (b[1] << 8);
1.4905 + given = (b[1]) | (b[0] << 8);
1.4909 + /* These bit patterns signal a four-byte Thumb
1.4911 + if ((given & 0xF800) == 0xF800
1.4912 + || (given & 0xF800) == 0xF000
1.4913 + || (given & 0xF800) == 0xE800)
1.4915 + status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
1.4917 + given = (b[0]) | (b[1] << 8) | (given << 16);
1.4919 + given = (b[1]) | (b[0] << 8) | (given << 16);
1.4921 + printer = print_insn_thumb32;
1.4926 + if (ifthen_address != pc)
1.4927 + find_ifthen_state (pc, info, little_code);
1.4931 + if ((ifthen_state & 0xf) == 0x8)
1.4932 + ifthen_next_state = 0;
1.4934 + ifthen_next_state = (ifthen_state & 0xe0)
1.4935 + | ((ifthen_state & 0xf) << 1);
1.4941 + info->memory_error_func (status, pc, info);
1.4944 + if (info->flags & INSN_HAS_RELOC)
1.4945 + /* If the instruction has a reloc associated with it, then
1.4946 + the offset field in the instruction will actually be the
1.4947 + addend for the reloc. (We are using REL type relocs).
1.4948 + In such cases, we can ignore the pc when computing
1.4949 + addresses, since the addend is not currently pc-relative. */
1.4952 + printer (pc, info, given);
1.4956 + ifthen_state = ifthen_next_state;
1.4957 + ifthen_address += size;
1.4963 +print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
1.4965 + /* Detect BE8-ness and record it in the disassembler info. */
1.4967 + if (info->flavour == bfd_target_elf_flavour
1.4968 + && info->section != NULL
1.4969 + && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
1.4970 + info->endian_code = BFD_ENDIAN_LITTLE;
1.4972 + return print_insn (pc, info, FALSE);
1.4976 +print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
1.4978 + return print_insn (pc, info, TRUE);
1.4982 +print_arm_disassembler_options (FILE *stream)
1.4986 + fprintf (stream, _("\n\
1.4987 +The following ARM specific disassembler options are supported for use with\n\
1.4990 + for (i = NUM_ARM_REGNAMES; i--;)
1.4991 + fprintf (stream, " reg-names-%s %*c%s\n",
1.4993 + (int)(14 - strlen (regnames[i].name)), ' ',
1.4994 + regnames[i].description);
1.4996 + fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
1.4997 + fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
lxdream 0.9.1