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lxdream 0.9.1
released Jun 29
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filename src/xlat/disasm/arm.h
changeset 1265:7c6c5d26fd2e
author nkeynes
date Tue Mar 06 12:42:33 2012 +1000 (8 years ago)
permissions -rw-r--r--
last change Merge ARM disassembler from binutils 2.22
file annotate diff log raw
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/xlat/disasm/arm.h Tue Mar 06 12:42:33 2012 +1000
1.3 @@ -0,0 +1,261 @@
1.4 +/* ARM assembler/disassembler support.
1.5 + Copyright 2004, 2010, 2011 Free Software Foundation, Inc.
1.6 +
1.7 + This file is part of GDB and GAS.
1.8 +
1.9 + GDB and GAS are free software; you can redistribute it and/or
1.10 + modify it under the terms of the GNU General Public License as
1.11 + published by the Free Software Foundation; either version 3, or (at
1.12 + your option) any later version.
1.13 +
1.14 + GDB and GAS are distributed in the hope that it will be useful, but
1.15 + WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1.17 + General Public License for more details.
1.18 +
1.19 + You should have received a copy of the GNU General Public License
1.20 + along with GDB or GAS; see the file COPYING3. If not, write to the
1.21 + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
1.22 + MA 02110-1301, USA. */
1.23 +
1.24 +/* The following bitmasks control CPU extensions: */
1.25 +#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
1.26 +#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
1.27 +#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
1.28 +#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
1.29 +#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
1.30 +#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
1.31 +#define ARM_EXT_V4T 0x00000040 /* Thumb. */
1.32 +#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
1.33 +#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
1.34 +#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
1.35 +#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
1.36 +#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
1.37 +#define ARM_EXT_V6 0x00001000 /* ARM V6. */
1.38 +#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
1.39 +/* 0x00004000 Was ARM V6Z. */
1.40 +#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
1.41 +#define ARM_EXT_DIV 0x00010000 /* Integer division. */
1.42 +/* The 'M' in Arm V7M stands for Microcontroller.
1.43 + On earlier architecture variants it stands for Multiply. */
1.44 +#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */
1.45 +#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */
1.46 +#define ARM_EXT_V7 0x00080000 /* Arm V7. */
1.47 +#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */
1.48 +#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */
1.49 +#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */
1.50 +#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */
1.51 +#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */
1.52 +#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
1.53 +#define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related),
1.54 + not in v7-M. */
1.55 +#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
1.56 +#define ARM_EXT_SEC 0x10000000 /* Security extensions. */
1.57 +#define ARM_EXT_OS 0x20000000 /* OS Extensions. */
1.58 +#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM
1.59 + state. */
1.60 +#define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */
1.61 +
1.62 +/* Co-processor space extensions. */
1.63 +#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
1.64 +#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
1.65 +#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */
1.66 +#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */
1.67 +
1.68 +#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
1.69 +#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */
1.70 +#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
1.71 +#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
1.72 +#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */
1.73 +#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
1.74 +#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
1.75 +#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
1.76 +#define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */
1.77 +#define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */
1.78 +#define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */
1.79 +#define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */
1.80 +#define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */
1.81 +#define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */
1.82 +#define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */
1.83 +
1.84 +/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
1.85 + defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
1.86 + ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
1.87 + three more to cover cores prior to ARM6. Finally, there are cores which
1.88 + implement further extensions in the co-processor space. */
1.89 +#define ARM_AEXT_V1 ARM_EXT_V1
1.90 +#define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2)
1.91 +#define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S)
1.92 +#define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3)
1.93 +#define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M)
1.94 +#define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4)
1.95 +#define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4)
1.96 +#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T)
1.97 +#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T)
1.98 +#define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5)
1.99 +#define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5)
1.100 +#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T)
1.101 +#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T)
1.102 +#define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP)
1.103 +#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E)
1.104 +#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J)
1.105 +#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6)
1.106 +#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K)
1.107 +#define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC)
1.108 +#define ARM_AEXT_V6ZK (ARM_AEXT_V6K | ARM_EXT_SEC)
1.109 +#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \
1.110 + | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \
1.111 + | ARM_EXT_V6_DSP )
1.112 +#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
1.113 +#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC)
1.114 +#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
1.115 +#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
1.116 +#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
1.117 +#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
1.118 +#define ARM_AEXT_NOTM \
1.119 + (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \
1.120 + | ARM_EXT_V6_DSP )
1.121 +#define ARM_AEXT_V6M_ONLY \
1.122 + ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM))
1.123 +#define ARM_AEXT_V6M \
1.124 + ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM))
1.125 +#define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS)
1.126 +#define ARM_AEXT_V7M \
1.127 + ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
1.128 + & ~(ARM_AEXT_NOTM))
1.129 +#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
1.130 +#define ARM_AEXT_V7EM \
1.131 + (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP)
1.132 +
1.133 +/* Processors with specific extensions in the co-processor space. */
1.134 +#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
1.135 +#define ARM_ARCH_IWMMXT \
1.136 + ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
1.137 +#define ARM_ARCH_IWMMXT2 \
1.138 + ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)
1.139 +
1.140 +#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
1.141 +#define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1)
1.142 +#define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2)
1.143 +#define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3)
1.144 +#define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
1.145 +#define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD)
1.146 +#define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
1.147 +#define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
1.148 +#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
1.149 +#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
1.150 + | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \
1.151 + | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
1.152 +#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
1.153 +
1.154 +/* Deprecated. */
1.155 +#define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE)
1.156 +
1.157 +#define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1)
1.158 +#define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA)
1.159 +
1.160 +#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
1.161 +#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1)
1.162 +#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2)
1.163 +#define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16)
1.164 +#define FPU_ARCH_VFP_V3D16_FP16 \
1.165 + ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16)
1.166 +#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3)
1.167 +#define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16)
1.168 +#define FPU_ARCH_VFP_V3xD ARM_FEATURE (0, FPU_VFP_V3xD)
1.169 +#define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16)
1.170 +#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1)
1.171 +#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
1.172 + ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1)
1.173 +#define FPU_ARCH_NEON_FP16 \
1.174 + ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16)
1.175 +#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
1.176 +#define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4)
1.177 +#define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16)
1.178 +#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16)
1.179 +#define FPU_ARCH_NEON_VFP_V4 \
1.180 + ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)
1.181 +
1.182 +#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)
1.183 +
1.184 +#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK)
1.185 +
1.186 +#define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0)
1.187 +#define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0)
1.188 +#define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0)
1.189 +#define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0)
1.190 +#define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0)
1.191 +#define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0)
1.192 +#define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0)
1.193 +#define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0)
1.194 +#define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0)
1.195 +#define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0)
1.196 +#define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0)
1.197 +#define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0)
1.198 +#define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0)
1.199 +#define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0)
1.200 +#define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0)
1.201 +#define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0)
1.202 +#define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0)
1.203 +#define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0)
1.204 +#define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0)
1.205 +#define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0)
1.206 +#define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0)
1.207 +#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0)
1.208 +#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
1.209 +#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
1.210 +#define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0)
1.211 +#define ARM_ARCH_V6SM ARM_FEATURE (ARM_AEXT_V6SM, 0)
1.212 +#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0)
1.213 +#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0)
1.214 +#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0)
1.215 +#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0)
1.216 +#define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0)
1.217 +
1.218 +/* Some useful combinations: */
1.219 +#define ARM_ARCH_NONE ARM_FEATURE (0, 0)
1.220 +#define FPU_NONE ARM_FEATURE (0, 0)
1.221 +#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */
1.222 +#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
1.223 +#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0)
1.224 +/* v7-a+sec. */
1.225 +#define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0)
1.226 +/* v7-a+mp+sec. */
1.227 +#define ARM_ARCH_V7A_MP_SEC \
1.228 + ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \
1.229 + 0)
1.230 +/* v7-a+idiv+mp+sec+virt. */
1.231 +#define ARM_ARCH_V7A_IDIV_MP_SEC_VIRT \
1.232 + ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \
1.233 + | ARM_EXT_DIV | ARM_EXT_ADIV \
1.234 + | ARM_EXT_VIRT, 0)
1.235 +/* v7-r+idiv. */
1.236 +#define ARM_ARCH_V7R_IDIV ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0)
1.237 +/* Features that are present in v6M and v6S-M but not other v6 cores. */
1.238 +#define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0)
1.239 +
1.240 +/* There are too many feature bits to fit in a single word, so use a
1.241 + structure. For simplicity we put all core features in one word and
1.242 + everything else in the other. */
1.243 +typedef struct
1.244 +{
1.245 + unsigned long core;
1.246 + unsigned long coproc;
1.247 +} arm_feature_set;
1.248 +
1.249 +#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
1.250 + (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0)
1.251 +
1.252 +#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \
1.253 + do { \
1.254 + (TARG).core = (F1).core | (F2).core; \
1.255 + (TARG).coproc = (F1).coproc | (F2).coproc; \
1.256 + } while (0)
1.257 +
1.258 +#define ARM_CLEAR_FEATURE(TARG,F1,F2) \
1.259 + do { \
1.260 + (TARG).core = (F1).core &~ (F2).core; \
1.261 + (TARG).coproc = (F1).coproc &~ (F2).coproc; \
1.262 + } while (0)
1.263 +
1.264 +#define ARM_FEATURE(core, coproc) {(core), (coproc)}
.