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lxdream.org :: lxdream/src/sh4/sh4x86.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 394:7eb172bfeefe
prev388:13bae2fb0373
next395:c473acbde186
author nkeynes
date Wed Sep 19 09:15:18 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Fix SUBC (not updating T), FTRC (not truncating), and XTRCT (just b0rked)
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.c Tue Sep 18 08:59:00 2007 +0000
1.2 +++ b/src/sh4/sh4x86.c Wed Sep 19 09:15:18 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4x86.c,v 1.10 2007-09-18 08:59:00 nkeynes Exp $
1.6 + * $Id: sh4x86.c,v 1.11 2007-09-19 09:15:18 nkeynes Exp $
1.7 *
1.8 * SH4 => x86 translation. This version does no real optimization, it just
1.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
1.10 @@ -61,6 +61,8 @@
1.11
1.12 static uint32_t max_int = 0x7FFFFFFF;
1.13 static uint32_t min_int = 0x80000000;
1.14 +static uint32_t save_fcw; /* save value for fpu control word */
1.15 +static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
1.16 void signsat48( void )
1.17 {
1.18 if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
1.19 @@ -838,6 +840,7 @@
1.20 call_func0( sh4_sleep );
1.21 sh4_x86.exit_code = 0;
1.22 sh4_x86.in_delay_slot = FALSE;
1.23 + INC_r32(R_ESI);
1.24 return 1;
1.25 }
1.26 break;
1.27 @@ -1067,9 +1070,9 @@
1.28 { /* XTRCT Rm, Rn */
1.29 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.30 load_reg( R_EAX, Rm );
1.31 - MOV_r32_r32( R_EAX, R_ECX );
1.32 - SHR_imm8_r32( 16, R_EAX );
1.33 - SHL_imm8_r32( 16, R_ECX );
1.34 + load_reg( R_ECX, Rn );
1.35 + SHL_imm8_r32( 16, R_EAX );
1.36 + SHR_imm8_r32( 16, R_ECX );
1.37 OR_r32_r32( R_EAX, R_ECX );
1.38 store_reg( R_ECX, Rn );
1.39 }
1.40 @@ -1196,6 +1199,7 @@
1.41 LDC_t();
1.42 SBB_r32_r32( R_EAX, R_ECX );
1.43 store_reg( R_ECX, Rn );
1.44 + SETC_t();
1.45 }
1.46 break;
1.47 case 0xB:
1.48 @@ -2480,7 +2484,7 @@
1.49 load_reg( R_ECX, R_GBR);
1.50 ADD_r32_r32( R_EAX, R_ECX );
1.51 MEM_READ_BYTE( R_ECX, R_EAX );
1.52 - TEST_imm8_r8( imm, R_EAX );
1.53 + TEST_imm8_r8( imm, R_AL );
1.54 SETE_t();
1.55 }
1.56 break;
1.57 @@ -2983,12 +2987,17 @@
1.58 load_imm32( R_ECX, (uint32_t)&max_int );
1.59 FILD_r32ind( R_ECX );
1.60 FCOMIP_st(1);
1.61 - JNA_rel8( 16, sat );
1.62 + JNA_rel8( 32, sat );
1.63 load_imm32( R_ECX, (uint32_t)&min_int ); // 5
1.64 FILD_r32ind( R_ECX ); // 2
1.65 FCOMIP_st(1); // 2
1.66 - JAE_rel8( 5, sat2 ); // 2
1.67 + JAE_rel8( 21, sat2 ); // 2
1.68 + load_imm32( R_EAX, (uint32_t)&save_fcw );
1.69 + FNSTCW_r32ind( R_EAX );
1.70 + load_imm32( R_EDX, (uint32_t)&trunc_fcw );
1.71 + FLDCW_r32ind( R_EDX );
1.72 FISTP_sh4r(R_FPUL); // 3
1.73 + FLDCW_r32ind( R_EAX );
1.74 JMP_rel8( 9, end ); // 2
1.75
1.76 JMP_TARGET(sat);
.