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lxdream.org :: lxdream/src/sh4/sh4x86.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 394:7eb172bfeefe
prev388:13bae2fb0373
next395:c473acbde186
author nkeynes
date Wed Sep 19 09:15:18 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Fix SUBC (not updating T), FTRC (not truncating), and XTRCT (just b0rked)
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.in Tue Sep 18 08:59:00 2007 +0000
1.2 +++ b/src/sh4/sh4x86.in Wed Sep 19 09:15:18 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4x86.in,v 1.11 2007-09-18 08:59:00 nkeynes Exp $
1.6 + * $Id: sh4x86.in,v 1.12 2007-09-19 09:15:18 nkeynes Exp $
1.7 *
1.8 * SH4 => x86 translation. This version does no real optimization, it just
1.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
1.10 @@ -61,6 +61,8 @@
1.11
1.12 static uint32_t max_int = 0x7FFFFFFF;
1.13 static uint32_t min_int = 0x80000000;
1.14 +static uint32_t save_fcw; /* save value for fpu control word */
1.15 +static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
1.16 void signsat48( void )
1.17 {
1.18 if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
1.19 @@ -964,6 +966,7 @@
1.20 LDC_t();
1.21 SBB_r32_r32( R_EAX, R_ECX );
1.22 store_reg( R_ECX, Rn );
1.23 + SETC_t();
1.24 :}
1.25 SUBV Rm, Rn {:
1.26 load_reg( R_EAX, Rm );
1.27 @@ -1010,7 +1013,7 @@
1.28 load_reg( R_ECX, R_GBR);
1.29 ADD_r32_r32( R_EAX, R_ECX );
1.30 MEM_READ_BYTE( R_ECX, R_EAX );
1.31 - TEST_imm8_r8( imm, R_EAX );
1.32 + TEST_imm8_r8( imm, R_AL );
1.33 SETE_t();
1.34 :}
1.35 XOR Rm, Rn {:
1.36 @@ -1036,9 +1039,9 @@
1.37 :}
1.38 XTRCT Rm, Rn {:
1.39 load_reg( R_EAX, Rm );
1.40 - MOV_r32_r32( R_EAX, R_ECX );
1.41 - SHR_imm8_r32( 16, R_EAX );
1.42 - SHL_imm8_r32( 16, R_ECX );
1.43 + load_reg( R_ECX, Rn );
1.44 + SHL_imm8_r32( 16, R_EAX );
1.45 + SHR_imm8_r32( 16, R_ECX );
1.46 OR_r32_r32( R_EAX, R_ECX );
1.47 store_reg( R_ECX, Rn );
1.48 :}
1.49 @@ -1761,12 +1764,17 @@
1.50 load_imm32( R_ECX, (uint32_t)&max_int );
1.51 FILD_r32ind( R_ECX );
1.52 FCOMIP_st(1);
1.53 - JNA_rel8( 16, sat );
1.54 + JNA_rel8( 32, sat );
1.55 load_imm32( R_ECX, (uint32_t)&min_int ); // 5
1.56 FILD_r32ind( R_ECX ); // 2
1.57 FCOMIP_st(1); // 2
1.58 - JAE_rel8( 5, sat2 ); // 2
1.59 + JAE_rel8( 21, sat2 ); // 2
1.60 + load_imm32( R_EAX, (uint32_t)&save_fcw );
1.61 + FNSTCW_r32ind( R_EAX );
1.62 + load_imm32( R_EDX, (uint32_t)&trunc_fcw );
1.63 + FLDCW_r32ind( R_EDX );
1.64 FISTP_sh4r(R_FPUL); // 3
1.65 + FLDCW_r32ind( R_EAX );
1.66 JMP_rel8( 9, end ); // 2
1.67
1.68 JMP_TARGET(sat);
1.69 @@ -2268,6 +2276,7 @@
1.70 call_func0( sh4_sleep );
1.71 sh4_x86.exit_code = 0;
1.72 sh4_x86.in_delay_slot = FALSE;
1.73 + INC_r32(R_ESI);
1.74 return 1;
1.75 :}
1.76 STC SR, Rn {:
.