filename | src/sh4/mmu.c |
changeset | 841:808d64b05073 |
prev | 826:69f2c9f1e608 |
next | 905:4c17ebd9ef5e |
author | nkeynes |
date | Tue Sep 02 11:53:16 2008 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Initial implementation of the performance counters, only working one for now is raw clock cycles (0x23) |
file | annotate | diff | log | raw |
1.1 --- a/src/sh4/mmu.c Sun Aug 24 02:43:28 2008 +00001.2 +++ b/src/sh4/mmu.c Tue Sep 02 11:53:16 2008 +00001.3 @@ -192,10 +192,12 @@1.4 val &= 0x0000001C;1.5 break;1.6 case PMCR1:1.7 + PMM_write_control(0, val);1.8 + val &= 0x0000C13F;1.9 + break;1.10 case PMCR2:1.11 - if( val != 0 ) {1.12 - WARN( "Performance counters not implemented" );1.13 - }1.14 + PMM_write_control(1, val);1.15 + val &= 0x0000C13F;1.16 break;1.17 default:1.18 break;1.19 @@ -964,19 +966,3 @@1.20 return TRUE;1.21 }1.23 -/********************************* PMM *************************************/1.24 -1.25 -/**1.26 - * Side note - this is here (rather than in sh4mmio.c) as the control registers1.27 - * are part of the MMU block, and it seems simplest to keep it all together.1.28 - */1.29 -1.30 -int32_t mmio_region_PMM_read( uint32_t reg )1.31 -{1.32 - return MMIO_READ( PMM, reg );1.33 -}1.34 -1.35 -void mmio_region_PMM_write( uint32_t reg, uint32_t val )1.36 -{1.37 - /* Read-only */1.38 -}
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