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lxdream.org :: lxdream/src/sh4/sh4x86.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 937:81b0c79d9788
prev936:f394309c399a
next939:6f2302afeb89
author nkeynes
date Sat Dec 27 03:14:59 2008 +0000 (13 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Update sh4x86 to take advantage of SR assumptions. nice 2% there :)
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.in Sat Dec 27 02:59:35 2008 +0000
1.2 +++ b/src/sh4/sh4x86.in Sat Dec 27 03:14:59 2008 +0000
1.3 @@ -53,7 +53,6 @@
1.4 */
1.5 struct sh4_x86_state {
1.6 int in_delay_slot;
1.7 - gboolean priv_checked; /* true if we've already checked the cpu mode. */
1.8 gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
1.9 gboolean branch_taken; /* true if we branched unconditionally */
1.10 gboolean double_prec; /* true if FPU is in double-precision mode */
1.11 @@ -238,17 +237,15 @@
1.12 /* Exception checks - Note that all exception checks will clobber EAX */
1.13
1.14 #define check_priv( ) \
1.15 - if( !sh4_x86.priv_checked ) { \
1.16 - sh4_x86.priv_checked = TRUE;\
1.17 - load_spreg( R_EAX, R_SR );\
1.18 - AND_imm32_r32( SR_MD, R_EAX );\
1.19 - if( sh4_x86.in_delay_slot ) {\
1.20 - JE_exc( EXC_SLOT_ILLEGAL );\
1.21 - } else {\
1.22 - JE_exc( EXC_ILLEGAL );\
1.23 - }\
1.24 - sh4_x86.tstate = TSTATE_NONE; \
1.25 - }\
1.26 + if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \
1.27 + if( sh4_x86.in_delay_slot ) { \
1.28 + JMP_exc(EXC_SLOT_ILLEGAL); \
1.29 + } else { \
1.30 + JMP_exc(EXC_ILLEGAL ); \
1.31 + } \
1.32 + sh4_x86.in_delay_slot = DELAY_NONE; \
1.33 + return 2; \
1.34 + }
1.35
1.36 #define check_fpuen( ) \
1.37 if( !sh4_x86.fpuen_checked ) {\
1.38 @@ -314,7 +311,7 @@
1.39 #define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
1.40 #endif
1.41
1.42 -#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
1.43 +#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
1.44
1.45 /****** Import appropriate calling conventions ******/
1.46 #if SIZEOF_VOID_P == 8
1.47 @@ -327,7 +324,6 @@
1.48 {
1.49 enter_block();
1.50 sh4_x86.in_delay_slot = FALSE;
1.51 - sh4_x86.priv_checked = FALSE;
1.52 sh4_x86.fpuen_checked = FALSE;
1.53 sh4_x86.branch_taken = FALSE;
1.54 sh4_x86.backpatch_posn = 0;
1.55 @@ -1752,7 +1748,6 @@
1.56 load_spreg( R_EAX, R_SSR );
1.57 call_func1( sh4_write_sr, R_EAX );
1.58 sh4_x86.in_delay_slot = DELAY_PC;
1.59 - sh4_x86.priv_checked = FALSE;
1.60 sh4_x86.fpuen_checked = FALSE;
1.61 sh4_x86.tstate = TSTATE_NONE;
1.62 sh4_x86.branch_taken = TRUE;
1.63 @@ -2323,9 +2318,9 @@
1.64 check_priv();
1.65 load_reg( R_EAX, Rm );
1.66 call_func1( sh4_write_sr, R_EAX );
1.67 - sh4_x86.priv_checked = FALSE;
1.68 sh4_x86.fpuen_checked = FALSE;
1.69 sh4_x86.tstate = TSTATE_NONE;
1.70 + return 2;
1.71 }
1.72 :}
1.73 LDC Rm, GBR {:
1.74 @@ -2397,9 +2392,9 @@
1.75 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.76 MEM_READ_LONG( R_EAX, R_EAX );
1.77 call_func1( sh4_write_sr, R_EAX );
1.78 - sh4_x86.priv_checked = FALSE;
1.79 sh4_x86.fpuen_checked = FALSE;
1.80 sh4_x86.tstate = TSTATE_NONE;
1.81 + return 2;
1.82 }
1.83 :}
1.84 LDC.L @Rm+, VBR {:
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