1.1 --- a/src/asic.c Mon Oct 08 12:09:06 2007 +0000
1.2 +++ b/src/asic.c Thu Dec 06 10:40:27 2007 +0000
1.9 MMIO_WRITE( ASIC, reg, val );
1.13 MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );
1.16 + MMIO_WRITE( EXTDMA, reg, val & 1 );
1.20 MMIO_WRITE( EXTDMA, reg, val & 0x01 );
1.21 @@ -478,34 +482,50 @@
1.22 idereg.interface_enabled = FALSE;
1.25 + case G2DMA0EXT: case G2DMA0SH4: case G2DMA0SIZ:
1.26 + case G2DMA1EXT: case G2DMA1SH4: case G2DMA1SIZ:
1.27 + case G2DMA2EXT: case G2DMA2SH4: case G2DMA2SIZ:
1.28 + case G2DMA3EXT: case G2DMA3SH4: case G2DMA3SIZ:
1.29 + MMIO_WRITE( EXTDMA, reg, val & 0x9FFFFFE0 );
1.31 + case G2DMA0MOD: case G2DMA1MOD: case G2DMA2MOD: case G2DMA3MOD:
1.32 + MMIO_WRITE( EXTDMA, reg, val & 0x07 );
1.34 + case G2DMA0DIR: case G2DMA1DIR: case G2DMA2DIR: case G2DMA3DIR:
1.35 + MMIO_WRITE( EXTDMA, reg, val & 0x01 );
1.39 - MMIO_WRITE( EXTDMA, reg, val );
1.40 + MMIO_WRITE( EXTDMA, reg, val & 1);
1.41 g2_dma_transfer( 0 );
1.44 + MMIO_WRITE( EXTDMA, reg, val & 0x37 );
1.48 - MMIO_WRITE( EXTDMA, reg, val );
1.49 + MMIO_WRITE( EXTDMA, reg, val & 1);
1.50 g2_dma_transfer( 1 );
1.54 + MMIO_WRITE( EXTDMA, reg, val & 0x37 );
1.58 - MMIO_WRITE( EXTDMA, reg, val );
1.59 + MMIO_WRITE( EXTDMA, reg, val &1 );
1.60 g2_dma_transfer( 2 );
1.63 + MMIO_WRITE( EXTDMA, reg, val & 0x37 );
1.67 - MMIO_WRITE( EXTDMA, reg, val );
1.68 + MMIO_WRITE( EXTDMA, reg, val &1 );
1.69 g2_dma_transfer( 3 );
1.72 + MMIO_WRITE( EXTDMA, reg, val & 0x37 );