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filename test/testregs.c
changeset 549:828d103ad115
prev343:bf4bf0da94cc
next561:533f6b478071
author nkeynes
date Thu Dec 06 10:40:27 2007 +0000 (16 years ago)
permissions -rw-r--r--
last change Fix testregs so it passes now
file annotate diff log raw 
     1.1 --- a/test/testregs.c	Wed Jan 31 11:00:25 2007 +0000

     1.2 +++ b/test/testregs.c	Thu Dec 06 10:40:27 2007 +0000

     1.3 @@ -37,26 +37,26 @@

     1.4      { 0xA05F6800, 0xFFFFFFFF, 0x13FFFFE0 },

     1.5      { 0xA05F6800, 0x00000000, 0x10000000 },

     1.6      { 0xA05F6804, 0xFFFFFFFF, 0x00FFFFE0 },

     1.7 -    { 0xA05F6808, 0xFFFFFFFF, 0x00000001 },

     1.8 -    { 0xA05F6808, 0x00000000, 0x00000000 },

     1.9 -    { 0xA05F680C, 0xFFFFFFFF, 0x00000000 },

    1.10 -    { 0xA05F7400, 0xFFFFFFFF, 0x00000000 },

    1.11 +//    { 0xA05F6808, 0xFFFFFFFF, 0x00000001 },

    1.12 +//    { 0xA05F6808, 0x00000000, 0x00000000 },  // DMA start

    1.13 +//    { 0xA05F680C, 0xFFFFFFFF, 0x00000000 },  // Not a register afaik

    1.14 +//    { 0xA05F7400, 0xFFFFFFFF, 0x00000000 },  // Not a register

    1.15      { 0xA05F7404, 0xFFFFFFFF, 0x1FFFFFE0 },

    1.16      { 0xA05F7404, 0x00000000, 0x00000000 },

    1.17      { 0xA05F7408, 0xFFFFFFFF, 0x01FFFFFE },

    1.18      { 0xA05F740C, 0xFFFFFFFF, 0x00000001 },

    1.19 -    { 0xA05F7410, 0xFFFFFFFF, 0x00000000 },

    1.20 +//    { 0xA05F7410, 0xFFFFFFFF, 0x00000000 },  // Not a register

    1.21      { 0xA05F7414, 0xFFFFFFFF, 0x00000001 },

    1.22 -    { 0xA05F7418, 0xFFFFFFFF, 0x00000001 },

    1.23 -    { 0xA05F741C, 0xFFFFFFFF, 0x00000000 },

    1.24 +//    { 0xA05F7418, 0xFFFFFFFF, 0x00000001 },  // DMA start

    1.25 +//    { 0xA05F741C, 0xFFFFFFFF, 0x00000000 },  // Not a register

    1.26      { 0xA05F7800, 0xFFFFFFFF, 0x9FFFFFE0 },

    1.27      { 0xA05F7800, 0x00000000, 0x00000000 },

    1.28      { 0xA05F7804, 0xFFFFFFFF, 0x9FFFFFE0 },

    1.29      { 0xA05F7808, 0xFFFFFFFF, 0x9FFFFFE0 },

    1.30 -    { 0xA05F780C, 0xFFFFFFFF, 0x00000001 },

    1.31 +    { 0xA05F780C, 0xFFFFFFFF, 0x00000001 }, 

    1.32      { 0xA05F7810, 0xFFFFFFFF, 0x00000007 },

    1.33      { 0xA05F7814, 0xFFFFFFFF, 0x00000001 },

    1.34 -    { 0xA05F7818, 0xFFFFFFFF, 0x00000000 },

    1.35 +//    { 0xA05F7818, 0xFFFFFFFF, 0x00000000 },  // DMA start

    1.36      { 0xA05F781C, 0xFFFFFFFF, 0x00000037 },

    1.37      { 0xA05F8000, 0xFFFFFFFF, 0x17FD11DB }, /* PVRID read-only */

    1.38      { 0xA05F8004, 0xFFFFFFFF, 0x00000011 }, /* PVRVER read-only */
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