Search
lxdream.org :: lxdream/src/sh4/sh4mem.c :: diff
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4mem.c
changeset 933:880c37bb1909
prev931:430048ea8b71
next934:3acd3b3ee6d1
author nkeynes
date Wed Dec 24 06:06:23 2008 +0000 (11 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Start putting cache together
file annotate diff log raw
1.1 --- a/src/sh4/sh4mem.c Tue Dec 23 05:48:05 2008 +0000
1.2 +++ b/src/sh4/sh4mem.c Wed Dec 24 06:06:23 2008 +0000
1.3 @@ -38,15 +38,15 @@
1.4 extern struct mem_region_fn mem_region_bootrom;
1.5
1.6 /* On-chip regions other than defined MMIO regions */
1.7 -extern struct mem_region_fn mem_region_storequeue;
1.8 -extern struct mem_region_fn mem_region_icache_addr;
1.9 -extern struct mem_region_fn mem_region_icache_data;
1.10 -extern struct mem_region_fn mem_region_ocache_addr;
1.11 -extern struct mem_region_fn mem_region_ocache_data;
1.12 -extern struct mem_region_fn mem_region_itlb_addr;
1.13 -extern struct mem_region_fn mem_region_itlb_data;
1.14 -extern struct mem_region_fn mem_region_utlb_addr;
1.15 -extern struct mem_region_fn mem_region_utlb_data;
1.16 +extern struct mem_region_fn p4_region_storequeue;
1.17 +extern struct mem_region_fn p4_region_icache_addr;
1.18 +extern struct mem_region_fn p4_region_icache_data;
1.19 +extern struct mem_region_fn p4_region_ocache_addr;
1.20 +extern struct mem_region_fn p4_region_ocache_data;
1.21 +extern struct mem_region_fn p4_region_itlb_addr;
1.22 +extern struct mem_region_fn p4_region_itlb_data;
1.23 +extern struct mem_region_fn p4_region_utlb_addr;
1.24 +extern struct mem_region_fn p4_region_utlb_data;
1.25
1.26 /********************* The main ram address space **********************/
1.27 static int32_t FASTCALL ext_sdram_read_long( sh4addr_t addr )
1.28 @@ -178,28 +178,6 @@
1.29 p4_storequeue_read_long, p4_storequeue_write_long,
1.30 unmapped_read_burst, unmapped_write_burst }; // No burst access.
1.31
1.32 -/* Cache access */
1.33 -struct mem_region_fn p4_region_icache_addr = {
1.34 - mmu_icache_addr_read, mmu_icache_addr_write,
1.35 - mmu_icache_addr_read, mmu_icache_addr_write,
1.36 - mmu_icache_addr_read, mmu_icache_addr_write,
1.37 - unmapped_read_burst, unmapped_write_burst };
1.38 -struct mem_region_fn p4_region_icache_data = {
1.39 - mmu_icache_data_read, mmu_icache_data_write,
1.40 - mmu_icache_data_read, mmu_icache_data_write,
1.41 - mmu_icache_data_read, mmu_icache_data_write,
1.42 - unmapped_read_burst, unmapped_write_burst };
1.43 -struct mem_region_fn p4_region_ocache_addr = {
1.44 - mmu_ocache_addr_read, mmu_ocache_addr_write,
1.45 - mmu_ocache_addr_read, mmu_ocache_addr_write,
1.46 - mmu_ocache_addr_read, mmu_ocache_addr_write,
1.47 - unmapped_read_burst, unmapped_write_burst };
1.48 -struct mem_region_fn p4_region_ocache_data = {
1.49 - mmu_ocache_data_read, mmu_ocache_data_write,
1.50 - mmu_ocache_data_read, mmu_ocache_data_write,
1.51 - mmu_ocache_data_read, mmu_ocache_data_write,
1.52 - unmapped_read_burst, unmapped_write_burst };
1.53 -
1.54 /* TLB access */
1.55 struct mem_region_fn p4_region_itlb_addr = {
1.56 mmu_itlb_addr_read, mmu_itlb_addr_write,
.