1.1 --- a/src/aica/armcore.c Tue Jan 17 12:53:39 2006 +0000
1.2 +++ b/src/aica/armcore.c Thu Jan 25 12:55:31 2007 +0000
1.5 - * $Id: armcore.c,v 1.19 2006-01-17 12:53:39 nkeynes Exp $
1.6 + * $Id: armcore.c,v 1.20 2006-01-22 22:40:05 nkeynes Exp $
1.8 * ARM7TDMI CPU emulation core.
1.11 uint32_t arm_run_slice( uint32_t num_samples )
1.15 + if( !armr.running )
1.16 + return num_samples;
1.18 for( i=0; i<num_samples; i++ ) {
1.19 for( j=0; j < CYCLES_PER_SAMPLE; j++ ) {
1.23 armr.cpsr = MODE_SVC | CPSR_I | CPSR_F;
1.24 armr.r[15] = 0x00000000;
1.25 + armr.running = TRUE;
1.28 #define SET_CPSR_CONTROL 0x00010000
1.38 * Condition passed, now for the actual instructions...
1.39 @@ -1369,9 +1373,12 @@
1.43 - if( armr.r[15] > 0x00200000 ) {
1.45 - ERROR( "BRANCH to fishkill at %08X", pc );
1.49 + if( armr.r[15] >= 0x00200000 ) {
1.50 + armr.running = FALSE;
1.51 + ERROR( "ARM Halted: BRANCH to invalid address %08X at %08X", armr.r[15], pc );