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lxdream.org :: lxdream/src/sh4/sh4core.h :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.h
changeset 374:8f80a795513e
prev369:4b4223e7d720
next378:f10fbdd4e24b
author nkeynes
date Tue Sep 11 02:14:46 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Cache the pointer to the last FR bank (speeds fp ops up by about 10%)
Implement experimental fix for FLOAT/FTRC
Make read/write sr functions non-static (share with translator)
Much more translator WIP
file annotate diff log raw
1.1 --- a/src/sh4/sh4core.h Sat Sep 08 03:12:21 2007 +0000
1.2 +++ b/src/sh4/sh4core.h Tue Sep 11 02:14:46 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4core.h,v 1.21 2007-09-08 03:12:21 nkeynes Exp $
1.6 + * $Id: sh4core.h,v 1.22 2007-09-11 02:14:46 nkeynes Exp $
1.7 *
1.8 * This file defines the internal functions exported/used by the SH4 core,
1.9 * except for disassembly functions defined in sh4dasm.h
1.10 @@ -58,14 +58,15 @@
1.11
1.12 struct sh4_registers {
1.13 uint32_t r[16];
1.14 + uint32_t sr, pr, pc, fpscr;
1.15 + uint32_t t, m, q, s; /* really boolean - 0 or 1 */
1.16 + int32_t fpul;
1.17 + float *fr_bank;
1.18 + float fr[2][16];
1.19 + uint64_t mac;
1.20 + uint32_t gbr, ssr, spc, sgr, dbr, vbr;
1.21 +
1.22 uint32_t r_bank[8]; /* hidden banked registers */
1.23 - uint32_t sr, pr, pc, fpscr, t;
1.24 - int32_t fpul;
1.25 - uint32_t gbr, ssr, spc, sgr, dbr, vbr;
1.26 - uint64_t mac;
1.27 - uint32_t m, q, s; /* really boolean - 0 or 1 */
1.28 - float fr[2][16];
1.29 -
1.30 int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
1.31
1.32 uint32_t new_pc; /* Not a real register, but used to handle delay slots */
1.33 @@ -111,6 +112,10 @@
1.34 int32_t sh4_read_phys_word( uint32_t addr );
1.35 void sh4_flush_store_queue( uint32_t addr );
1.36
1.37 +/* SH4 Support methods */
1.38 +uint32_t sh4_read_sr(void);
1.39 +void sh4_write_sr(uint32_t val);
1.40 +
1.41 /* Peripheral functions */
1.42 void CPG_reset( void );
1.43 void TMU_run_slice( uint32_t );
1.44 @@ -171,8 +176,8 @@
1.45 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
1.46 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
1.47
1.48 -#define FR(x) sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][(x)^1]
1.49 -#define DRF(x) ((double *)(sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]))[x]
1.50 +#define FR(x) sh4r.fr_bank[(x)^1]
1.51 +#define DRF(x) ((double *)sh4r.fr_bank)[x]
1.52 #define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1]
1.53 #define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x]
1.54 #define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x]
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