1.1 --- a/src/aica/armcore.c Sat Oct 02 05:49:23 2004 +0000
1.2 +++ b/src/aica/armcore.c Sun Dec 12 07:44:09 2004 +0000
1.5 -#include "armcore.h"
1.6 +#include "aica/armcore.h"
1.8 struct arm_registers armr;
1.11 #define IS_SUBOVERFLOW( result, op1, op2 ) (((op1^op2) & (result^op1)) >> 31)
1.12 #define IS_ADDOVERFLOW( result, op1, op2 ) (((op1&op2) & (result^op1)) >> 31)
1.14 -#define PC armr.r[15];
1.15 +#define PC armr.r[15]
1.17 /* Instruction fields */
1.18 #define COND(ir) (ir>>28)
1.21 #define IMM8(ir) (ir&0xFF)
1.22 #define IMM12(ir) (ir&0xFFF)
1.23 -#define SHIFTIMM(ir) ((ir>>7)0x1F)
1.24 -#define IMMROT(ir) ((ir>>7)&1E)
1.25 +#define SHIFTIMM(ir) ((ir>>7)&0x1F)
1.26 +#define IMMROT(ir) ((ir>>7)&0x1E)
1.27 #define SHIFT(ir) ((ir>>4)&0x07)
1.28 #define DISP24(ir) ((ir&0x00FFFFFF))
1.29 +#define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", PC, ir ); return; } while(0)
1.30 +#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", PC, ir ); return; }while(0)
1.33 static uint32_t arm_get_shift_operand( uint32_t ir )
1.38 if( tmp == 0 ) /* RRX aka rotate with carry */
1.39 - operand = (operand >> 1) | (arm4.c<<31);
1.40 + operand = (operand >> 1) | (armr.c<<31);
1.42 operand = ROTATE_RIGHT_LONG(operand,tmp);
1.46 if( tmp == 0 ) { /* RRX aka rotate with carry */
1.47 armr.shift_c = operand&0x01;
1.48 - operand = (operand >> 1) | (arm4.c<<31);
1.49 + operand = (operand >> 1) | (armr.c<<31);
1.51 armr.shift_c = operand>>(tmp-1);
1.52 operand = ROTATE_RIGHT_LONG(operand,tmp);
1.54 static uint32_t arm_get_address_index( uint32_t ir )
1.56 uint32_t operand = RM(ir);
1.60 case 0: /* (Rm << imm) */
1.61 operand = operand << SHIFTIMM(ir);
1.65 if( tmp == 0 ) /* RRX aka rotate with carry */
1.66 - operand = (operand >> 1) | (arm4.c<<31);
1.67 + operand = (operand >> 1) | (armr.c<<31);
1.69 operand = ROTATE_RIGHT_LONG(operand,tmp);
1.71 @@ -262,50 +267,50 @@
1.72 case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
1.75 - RN(ir) = addr - IMM12(ir);
1.76 + LRN(ir) = addr - IMM12(ir);
1.78 case 4: /* Rn += imm offsett (post-indexed) [5.2.8 A5-28] */
1.81 - RN(ir) = addr + IMM12(ir);
1.82 + LRN(ir) = addr + IMM12(ir);
1.84 case 8: /* Rn - imm offset [5.2.2 A5-20] */
1.85 addr = RN(ir) - IMM12(ir);
1.87 case 9: /* Rn -= imm offset (pre-indexed) [5.2.5 A5-24] */
1.88 addr = RN(ir) - IMM12(ir);
1.92 case 12: /* Rn + imm offset [5.2.2 A5-20] */
1.93 addr = RN(ir) + IMM12(ir);
1.95 case 13: /* Rn += imm offset [5.2.5 A5-24 ] */
1.96 addr = RN(ir) + IMM12(ir);
1.100 case 16: /* Rn -= Rm (post-indexed) [5.2.10 A5-32 ] */
1.103 - RN(ir) = addr - arm_get_address_index(ir);
1.104 + LRN(ir) = addr - arm_get_address_index(ir);
1.106 case 20: /* Rn += Rm (post-indexed) [5.2.10 A5-32 ] */
1.109 - RN(ir) = addr - arm_get_address_index(ir);
1.110 + LRN(ir) = addr - arm_get_address_index(ir);
1.112 case 24: /* Rn - Rm [5.2.4 A5-23] */
1.113 addr = RN(ir) - arm_get_address_index(ir);
1.115 case 25: /* RN -= Rm (pre-indexed) [5.2.7 A5-26] */
1.116 addr = RN(ir) - arm_get_address_index(ir);
1.120 case 28: /* Rn + Rm [5.2.4 A5-23] */
1.121 addr = RN(ir) + arm_get_address_index(ir);
1.123 case 29: /* RN += Rm (pre-indexed) [5.2.7 A5-26] */
1.124 addr = RN(ir) + arm_get_address_index(ir);
1.129 UNIMP(ir); /* Unreachable */
1.130 @@ -316,8 +321,8 @@
1.131 void arm_execute_instruction( void )
1.134 - uint32_t ir = MEM_READ_LONG(PC);
1.135 - uint32_t operand, operand2, tmp, armr.shift_c;
1.136 + uint32_t ir = MEM_READ_LONG(pc);
1.137 + uint32_t operand, operand2, tmp, cond;
1.141 @@ -393,7 +398,7 @@
1.142 case 0x03600000: /* MSR SPSR, imm */
1.148 } else if( (ir & 0x0E000090) == 0x00000090 ) {
1.149 /* Neither are these */
1.150 @@ -460,11 +465,11 @@
1.152 switch(OPCODE(ir)) {
1.153 case 0: /* AND Rd, Rn, operand */
1.154 - RD(ir) = RN(ir) & arm_get_shift_operand(ir);
1.155 + LRD(ir) = RN(ir) & arm_get_shift_operand(ir);
1.157 case 1: /* ANDS Rd, Rn, operand */
1.158 operand = arm_get_shift_operand_s(ir) & RN(ir);
1.159 - RD(ir) = operand;
1.160 + LRD(ir) = operand;
1.161 if( RDn(ir) == 15 ) {
1.162 arm_restore_cpsr();
1.164 @@ -474,11 +479,11 @@
1.167 case 2: /* EOR Rd, Rn, operand */
1.168 - RD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
1.169 + LRD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
1.171 case 3: /* EORS Rd, Rn, operand */
1.172 operand = arm_get_shift_operand_s(ir) ^ RN(ir);
1.173 - RD(ir) = operand;
1.174 + LRD(ir) = operand;
1.175 if( RDn(ir) == 15 ) {
1.176 arm_restore_cpsr();
1.178 @@ -488,13 +493,13 @@
1.181 case 4: /* SUB Rd, Rn, operand */
1.182 - RD(ir) = RN(ir) - arm_get_shift_operand(ir);
1.183 + LRD(ir) = RN(ir) - arm_get_shift_operand(ir);
1.185 case 5: /* SUBS Rd, Rn, operand */
1.187 - operand2 = arm_get_shift_operand(ir)
1.188 + operand2 = arm_get_shift_operand(ir);
1.189 tmp = operand - operand2;
1.192 if( RDn(ir) == 15 ) {
1.193 arm_restore_cpsr();
1.195 @@ -505,13 +510,13 @@
1.198 case 6: /* RSB Rd, operand, Rn */
1.199 - RD(ir) = arm_get_shift_operand(ir) - RN(ir);
1.200 + LRD(ir) = arm_get_shift_operand(ir) - RN(ir);
1.202 case 7: /* RSBS Rd, operand, Rn */
1.203 operand = arm_get_shift_operand(ir);
1.205 tmp = operand - operand2;
1.208 if( RDn(ir) == 15 ) {
1.209 arm_restore_cpsr();
1.211 @@ -522,13 +527,13 @@
1.214 case 8: /* ADD Rd, Rn, operand */
1.215 - RD(ir) = RN(ir) + arm_get_shift_operand(ir);
1.216 + LRD(ir) = RN(ir) + arm_get_shift_operand(ir);
1.218 case 9: /* ADDS Rd, Rn, operand */
1.219 operand = arm_get_shift_operand(ir);
1.221 - tmp = operand + operand2
1.223 + tmp = operand + operand2;
1.225 if( RDn(ir) == 15 ) {
1.226 arm_restore_cpsr();
1.228 @@ -559,7 +564,7 @@
1.230 case 21: /* CMP Rn, operand */
1.232 - operand2 = arm_get_shift_operand(ir)
1.233 + operand2 = arm_get_shift_operand(ir);
1.234 tmp = operand - operand2;
1.236 armr.z = (tmp == 0);
1.237 @@ -568,7 +573,7 @@
1.239 case 23: /* CMN Rn, operand */
1.241 - operand2 = arm_get_shift_operand(ir)
1.242 + operand2 = arm_get_shift_operand(ir);
1.243 tmp = operand + operand2;
1.245 armr.z = (tmp == 0);
1.246 @@ -576,11 +581,11 @@
1.247 armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
1.249 case 24: /* ORR Rd, Rn, operand */
1.250 - RD(ir) = RN(ir) | arm_get_shift_operand(ir);
1.251 + LRD(ir) = RN(ir) | arm_get_shift_operand(ir);
1.253 case 25: /* ORRS Rd, Rn, operand */
1.254 operand = arm_get_shift_operand_s(ir) | RN(ir);
1.255 - RD(ir) = operand;
1.256 + LRD(ir) = operand;
1.257 if( RDn(ir) == 15 ) {
1.258 arm_restore_cpsr();
1.260 @@ -590,11 +595,11 @@
1.263 case 26: /* MOV Rd, operand */
1.264 - RD(ir) = arm_get_shift_operand(ir);
1.265 + LRD(ir) = arm_get_shift_operand(ir);
1.267 case 27: /* MOVS Rd, operand */
1.268 operand = arm_get_shift_operand_s(ir);
1.269 - RD(ir) = operand;
1.270 + LRD(ir) = operand;
1.271 if( RDn(ir) == 15 ) {
1.272 arm_restore_cpsr();
1.274 @@ -604,11 +609,11 @@
1.277 case 28: /* BIC Rd, Rn, operand */
1.278 - RD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
1.279 + LRD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
1.281 case 29: /* BICS Rd, Rn, operand */
1.282 operand = RN(ir) & (~arm_get_shift_operand_s(ir));
1.283 - RD(ir) = operand;
1.284 + LRD(ir) = operand;
1.285 if( RDn(ir) == 15 ) {
1.286 arm_restore_cpsr();
1.288 @@ -618,11 +623,11 @@
1.291 case 30: /* MVN Rd, operand */
1.292 - RD(ir) = ~arm_get_shift_operand(ir);
1.293 + LRD(ir) = ~arm_get_shift_operand(ir);
1.295 case 31: /* MVNS Rd, operand */
1.296 operand = ~arm_get_shift_operand_s(ir);
1.297 - RD(ir) = operand;
1.298 + LRD(ir) = operand;
1.299 if( RDn(ir) == 15 ) {
1.300 arm_restore_cpsr();
1.302 @@ -644,4 +649,3 @@